11.8. Events

Table 11.24 shows the events that are generated and the numbers that the PMU uses to reference the events. The table also shows the bit position of each event on the event bus. Event reference numbers that are not listed are reserved.

Table 11.24. PMU events

Event numberEvent mnemonicPMUEVENTx[24:0] bus[a]PMU event bus (to trace)[a]Event name
0x00SW_INCR-[0]Instruction architecturally executed (condition check pass) - Software increment
0x01L1I_CACHE_REFILL[0][1]Level 1 instruction cache refill
0x02L1I_TLB_REFILL[1][2]Level 1 instruction TLB refill
0x03L1D_CACHE_REFILL[2][3]Level 1 data cache refill
0x04L1D_CACHE-[5:4]Level 1 data cache access
0x05L1D_TLB_REFILL-[7:6]Level 1 data TLB refill
0x08INST_RETIRED[6:3][11:8]Instruction architecturally executed
0x09EXC_TAKEN[7][12]Exception taken
0x0AEXC_RETURN[8][13]Instruction architecturally executed (condition check pass) - Exception return
0x0BCID_WRITE_RETIRED-[14]Instruction architecturally executed (condition check pass) - Write to CONTEXTIDR
0x10BR_MIS_PRED[9][15]Mispredicted or not predicted branch speculatively executed
0x11CPU_CYCLES-[16]Cycle
0x12BR_PRED[10][17]Predictable branch speculatively executed
0x13MEM_ACCESS-[19:18]Data memory access
0x14L1I_CACHE[11][20]Level 1 instruction cache access
0x15L1D_CACHE_WB[12][21]Level 1 data cache Write-Back
0x16L2D_CACHE-[23:22]Level 2 data cache access
0x17L2D_CACHE_REFILL[13][24]Level 2 data cache refill
0x18L2D_CACHE_WB[14][25]Level 2 data cache Write-Back
0x19BUS_ACCESS-[27:26]Bus access
0x1AMEMORY_ERROR-[28]Local memory error
0x1BINST_SPEC-[30:29]Operation speculatively executed
0x1CTTBR_WRITE_RETIRED-[31]Instruction architecturally executed (condition check pass) - Write to translation table base
0x1DBUS_CYCLES-[32]Bus cycle
0x1ECHAIN-[33]Odd performance counter chain mode
0x40L1D_CACHE_LD[15][34]Level 1 data cache access - Read
0x41L1D_CACHE_ST[16][35]Level 1 data cache access - Write
0x42L1D_CACHE_REFILL_LD-[36]Level 1 data cache refill - Read
0x43L1D_CACHE_REFILL_ST-[37]Level 1 data cache refill - Write
0x46L1D_CACHE_WB_VICTIM-[38]Level 1 data cache Write-back - Victim
0x47L1D_CACHE_WB_CLEAN-[39]Level 1 data cache Write-back - Cleaning and coherency
0x48L1D_CACHE_INVAL-[40]Level 1 data cache invalidate
0x4CL1D_TLB_REFILL_LD[17][41]Level 1 data TLB refill - Read
0x4DL1D_TLB_REFILL_ST[18][42]Level 1 data TLB refill - Write
0x50L2D_CACHE_LD[19][43]Level 2 data cache access - Read
0x51L2D_CACHE_ST[20][44]Level 2 data cache access - Write
0x52L2D_CACHE_REFILL_LD-[45]Level 2 data cache refill - Read
0x53L2D_CACHE_REFILL_ST-[46]Level 2 data cache refill - Write
0x56L2D_CACHE_WB_VICTIM-[47]Level 2 data cache Write-back - Victim
0x57L2D_CACHE_WB_CLEAN-[48]Level 2 data cache Write-back - Cleaning and coherency
0x58L2D_CACHE_INVAL-[49]Level 2 data cache invalidate
0x60BUS_ACCESS_LD-[50]Bus access - Read
0x61BUS_ACCESS_ST-[51]Bus access - Write
0x62BUS_ACCESS_SHARED-[53:52]Bus access - Normal
0x63BUS_ACCESS_NOT_SHARED-[55:54]Bus access - Not normal
0x64BUS_ACCESS_NORMAL-[57:56]Bus access - Normal
0x65BUS_ACCESS_PERIPH-[59:58]Bus access - Peripheral
0x66MEM_ACCESS_LD-[60]Data memory access - Read
0x67MEM_ACCESS_ST-[61]Data memory access - Write
0x68[b]UNALIGNED_LD_SPEC-[62]Unaligned access - Read
0x69[b]UNALIGNED_ST_SPEC-[63]Unaligned access - Write
0x6A[b]UNALIGNED_LDST_SPEC-[65:64]Unaligned access
0x6CLDREX_SPEC[21][66]Exclusive operation speculatively executed - LDREX
0x6DSTREX_PASS_SPEC[22][67]Exclusive instruction speculatively executed - STREX pass
0x6ESTREX_FAIL_SPEC[23][68]Exclusive operation speculatively executed - STREX fail
0x70LD_SPEC-[70:69]Operation speculatively executed - Load
0x71ST_SPEC-[72:71]Operation speculatively executed - Store
0x72LDST_SPEC-[74:73]Operation speculatively executed - Load or store
0x73DP_SPEC-[76:75]Operation speculatively executed - Integer data processing
0x74ASE_SPEC-[78:77]Operation speculatively executed - Advanced SIMD
0x75VFP_SPEC-[80:79]Operation speculatively executed - VFP
0x76PC_WRITE_SPEC-[82:81]Operation speculatively executed - Software change of the PC
0x77CRYPTO_SPEC-[84:83]Operation speculatively executed, crypto data processing
0x78BR_IMMED_SPEC-[85]Branch speculatively executed - Immediate branch
0x79BR_RETURN_SPEC-[86]Branch speculatively executed - Procedure return
0x7ABR_INDIRECT_SPEC-[87]Branch speculatively executed - Indirect branch
0x7CISB_SPEC-[88]Barrier speculatively executed - ISB
0x7DDSB_SPEC[24][89]Barrier speculatively executed - DSB
0x7EDMB_SPEC[24][90]Barrier speculatively executed - DMB
0x81EXC_UNDEF-[91]Exception taken, other synchronous
0x82EXC_SVC-[92]Exception taken, Supervisor Call
0x83EXC_PABORT-[93]Exception taken, Instruction Abort
0x84EXC_DABORT-[94]Exception taken, Data Abort or SError
0x86EXC_IRQ-[95]Exception taken, IRQ
0x87EXC_FIQ-[96]Exception taken, FIQ
0x88EXC_SMC-[97]Exception taken, Secure Monitor Call
0x8AEXC_HVC-[98]Exception taken, Hypervisor Call
0x8BEXC_TRAP_PABORT-[99]Exception taken, Instruction Abort not taken locally
0x8CEXC_TRAP_DABORT-[100]Exception taken, Data Abort, or SError not taken locally
0x8DEXC_TRAP_OTHER-[101]Exception taken - Other traps not taken locally
0x8EEXC_TRAP_IRQ-[102]Exception taken, IRQ not taken locally
0x8FEXC_TRAP_FIQ-[103]Exception taken, FIQ not taken locally
0x90RC_LD_SPEC-[104]Release consistency instruction speculatively executed - Load-Acquire
0x91RC_ST_SPEC-[105]Release consistency instruction speculatively executed - Store-Release

[a] Event count is encoded as a plain binary number to accommodate count values of more than one in the same cycle.

[b] For this event, unaligned access means data access related memory operation that crosses line boundary.


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