11.7.12. PMU Peripheral Identification Registers

The PMU Peripheral Identification Registers provide standard information required for all components that conform to the ARM PMUv3 architecture. There is a set of eight registers, listed in register number order in Table 11.13.

Table 11.13. Summary of the PMU Peripheral Identification Registers

RegisterValueOffset
PMPIDR40x040xFD0
PMPIDR50x000xFD4
PMPIDR60x000xFD8
PMPIDR70x000xFDC
PMPIDR00xD70xFE0
PMPIDR10xB90xFE4
PMPIDR20x2B0xFE8
PMPIDR30x000xFEC

Only bits[7:0] of each PMU Peripheral ID Register are used, with bits[31:8] reserved. Together, the eight PMU Peripheral ID Registers define a single 64-bit Peripheral ID.

The PMU Peripheral ID registers are:

PMU Peripheral Identification Register 0

The PMPIDR0 characteristics are:

Purpose

Provides information to identify a Performance Monitors component.

Usage constraints

The PMPIDR0 can be accessed through the internal memory-mapped interface and the external debug interface.

The accessibility to the PMPIDR0 by condition code is:

OffDLKOSLKEPMADSLKDefault
----RORO

Table 11.1 describes the condition codes.

Configurations

The PMPIDR0 is in the Debug power domain.

Attributes

See the register summary in Table 11.7.

Figure 11.9 shows the PMPIDR0 bit assignments.

Figure 11.9. PMPIDR0 bit assignments

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Table 11.14 shows the PMPIDR0 bit assignments.

Table 11.14. PMPIDR0 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0

[7:0]Part_0
0xD7

Least significant byte of the performance monitor part number


The PMPIDR0 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFE0.

PMU Peripheral Identification Register 1

The PMPIDR1 characteristics are:

Purpose

Provides information to identify a Performance Monitors component.

Usage constraints

The PMPIDR1 can be accessed through the internal memory-mapped interface and the external debug interface.

The accessibility to the PMPIDR1 by condition code is:

OffDLKOSLKEPMADSLKDefault
----RORO

Table 11.1 describes the condition codes.

Configurations

The PMPIDR1 is in the Debug power domain.

Attributes

See the register summary in Table 11.7.

Figure 11.10 shows the PMPIDR1 bit assignments.

Figure 11.10. PMPIDR1 bit assignments

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Table 11.15 shows the PMPIDR1 bit assignments.

Table 11.15. PMPIDR1 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0.

[7:4]DES_0
0xB

ARM Limited. This is the least significant nibble of JEP106 ID code.

[3:0]Part_1
0x9

Most significant nibble of the performance monitor part number.


The PMPIDR1 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFE4.

PMU Peripheral Identification Register 2

The PMPIDR2 characteristics are:

Purpose

Provides information to identify a Performance Monitors component.

Usage constraints

The accessibility to the PMPIDR2 by condition code is:

OffDLKOSLKEPMADSLKDefault
----RORO

Table 11.1 describes the condition codes.

The PMPIDR2 can be accessed through the internal memory-mapped interface and the external debug interface.

Configurations

The PMPIDR2 is in the Debug power domain.

Attributes

See the register summary in Table 11.7.

Figure 11.11 shows the PMPIDR2 bit assignments.

Figure 11.11. PMPIDR2 bit assignments

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Table 11.16 shows the PMPIDR2 bit assignments.

Table 11.16. PMPIDR2 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0.

[7:4]Revision
0x2

Part major revision.

[3]JEDEC
0b1

RAO. Indicates a JEP106 identity code is used.

[2:0]DES_1
0b011

ARM Limited. This is the most significant nibble of JEP106 ID code.


The PMPIDR2 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFE8.

PMU Peripheral Identification Register 3

The PMPIDR3 characteristics are:

Purpose

Provides information to identify a Performance Monitors component.

Usage constraints

The PMPIDR3 can be accessed through the internal memory-mapped interface and the external debug interface.

The accessibility to the PMPIDR3 by condition code is:

OffDLKOSLKEPMADSLKDefault
----RORO

Table 11.1 describes the condition codes.

Configurations

The PMPIDR3 is in the Debug power domain.

Attributes

See the register summary in Table 11.7.

Figure 11.12 shows the PMPIDR3 bit assignments.

Figure 11.12. PMPIDR3 bit assignments

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Table 11.17 shows the PMPIDR3 bit assignments.

Table 11.17. PMPIDR3 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0

[7:4]REVAND
0x0

Part minor revision

[3:0]CMOD
0x0

Customer modified


The PMPIDR3 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFEC.

PMU Peripheral Identification Register 4

The PMPIDR4 characteristics are:

Purpose

Provides information to identify a Performance Monitors component.

Usage constraints

PMPIDR4 can be accessed through the internal memory-mapped interface and the external debug interface.

The accessibility to the PMPIDR4 by condition code is:

OffDLKOSLKEPMADSLKDefault
----RORO

Table 11.1 describes the condition codes.

Configurations

The PMPIDR4 is in the Debug power domain.

Attributes

See the register summary in Table 11.7.

Figure 11.13 shows the PMPIDR4 bit assignments.

Figure 11.13. PMPIDR4 bit assignments

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Table 11.18 shows the PMPIDR4 bit assignments.

Table 11.18. PMPIDR4 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0.

[7:4]Size
0x0

Size of the component. Log2 the number of 4KB pages from the start of the component to the end of the PMU Component ID registers.

[3:0]DES_2
0x4

ARM Limited. This is the least significant nibble JEP106 continuation code.


The PMPIDR4 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFD0.

PMU Peripheral Identification Register 5-7

No information is held in the Peripheral ID5, Peripheral ID6, and Peripheral ID7 Registers. They are reserved for future use and are res0.

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