11.4.2. Performance Monitors Common Event Identification Register 0, EL0

The PMCEID0_EL0 characteristics are:

Purpose

Defines which common architectural and common micro-architectural feature events are implemented.

Usage constraints

The accessibility to the PMCEID0_EL0 by Exception level is:

EL0 (NS)EL0 (S)EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
ConfigConfigRORORORORO

The external accessibility to the PMCEID0_EL0 by condition code is:

OffDLKOSLKEPMADSLKDefault
ErrorErrorErrorErrorRORO

Table 11.1 describes the condition codes.

Configurations

The PMCEID0_EL0 is Common to Secure and Non-secure states and architecturally mapped to:

  • The AArch32 PMCEID0 register.

  • The external PMCEID0_EL0 register.

Attributes

See the register summary in Table 11.3.

Figure 11.3 shows the PMCEID0_EL0 bit assignments

Figure 11.3. PMCEID0_EL0 bit assignments

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Table 11.5 shows the PMCEID0_EL0 bit assignments with event implemented or not implemented when the associated bit is set to 1 or 0.

PMCEID1_EL0[31:0] is reserved.

Table 11.5. Common Event Identification Register 0 bit assignments

BitNameEvent numberValueEvent implemented if bit set to 1 or not implemented if bit set to 0
[31]-0x1F0Reserved, res0.
[30]CH0x1E1Chain.[a] An odd-numbered counter increments when an overflow occurs on the preceding even-numbered counter. For even-numbered counters, does not count.
[29]BC0x1D1Bus cycle.
[28]TW0x1C1TTBR write, architecturally executed, condition check pass - write to translation table base.
[27]IS0x1B1Instruction speculatively executed.
[26]ME0x1A1Local memory error.
[25]BA0x191Bus access.
[24]DC2W0x181Level 2 data cache Write-Back.
[23]DC2R0x171Level 2 data cache refill.
[22]DC2A0x161Level 2 data cache access.
[21]DC1W0x151Level 1 data cache Write-Back.
[20]IC1A0x141Level 1 instruction cache access.
[19]MA0x131Data memory access.
[18]BP0x121Predictable branch speculatively executed.
[17]CC0x111Cycle.
[16]BM0x101Mispredicted or not predicted branch speculatively executed.
[15]UL0x0F0Instruction architecturally executed, condition check pass - unaligned load or store.
[14]BR0x0E0Instruction architecturally executed, condition check pass - procedure return.
[13]BI0x0D0Instruction architecturally executed - immediate branch.
[12]PW0x0C0Instruction architecturally executed, condition check pass - software change of the PC.
[11]CW0x0B1Instruction architecturally executed, condition check pass - write to CONTEXTIDR.
[10]ER0x0A1Instruction architecturally executed, condition check pass - exception return.
[9]ET0x091Exception taken.
[8]IA0x081Instruction architecturally executed.
[7]ST0x070Instruction architecturally executed, condition check pass - store.
[6]LD0x060Instruction architecturally executed, condition check pass - load.
[5]DT1R0x051Level 1 data TLB refill.This event is implemented.
[4]DC1A0x041Level 1 data cache access.
[3]DC1R0x031Level 1 data cache refill.
[2]IT1R0x021Level 1 instruction TLB refill.
[1]IC1R0x011Level 1 instruction cache refill.
[0]SI0x001Instruction architecturally executed, condition check pass - software increment.

[a] See the ARM® Architecture Reference Manual ARMv8 for more information about the chain event.


To access the PMCEID0_EL0 in AArch64 state, read or write the register with:

MRS <Xt>, PMCEID0_EL0; Read Performance Monitors Common Event Identification Register 0

To access the PMCEID0 in AArch32 state, read or write the CP15 register with:

MRC p15, 0, <Rt>, c9, c12, 6; Read Performance Monitors Common Event Identification Register 0

The PMCEID0_EL0 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xE20.

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