11.7.10. Performance Monitors Snapshot Reset Register

The PMSRR characteristics are:

Purpose

Reset the cycle counter and the performance counters.

Usage constraints

The external accessibility to the PMSRR by condition code is:

OffDLKOSLKEPMADSLKDefault
ErrorErrorRWRWRWRW

Table 11.1 describes the condition codes.

Configurations

There is no configuration information for PMSRR.

Attributes

See the register summary in Table 11.7.

Figure 11.7 shows the PMSRR bit assignments.

Figure 11.7. PMSRR bit assignments

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Table 11.11 shows the PMSRR bit assignments.

Table 11.11. PMSRR bit assignments

BitsNameFunction
[31]RC

Reset cycle counter. Indicates whether the PMCCNTR_EL0 and PMOVSR[31] are reset after a capture:

0

PMCCNTR_EL0 and PMOVSR[31] are not reset on capture.

1

PMCCNTR_EL0 and PMOVSR[31] are reset on capture.

[30:6]-Reserved, res0.
[5]RP5

Reset performance counter 5. Indicates whether PMEVCNTR5_EL0 and PMOVSR[5] are reset after a capture:

0

PMEVCNTR5_EL0 and PMOVSR[5] are not reset on capture.

1

PMEVCNTR5_EL0 and PMOVSR[5] are reset on capture.

[4]RP4

Reset performance counter 4. Indicates whether PMEVCNTR4_EL0 and PMOVSR[4] are reset after a capture:

0

PMEVCNTR4_EL0 and PMOVSR[4] are not reset on capture.

1

PMEVCNTR4_EL0 and PMOVSR[4] are reset on capture.

[3]RP3

Reset performance counter 3. Indicates whether PMEVCNTR3_EL0 and PMOVSR[3] are reset after a capture:

0

PMEVCNTR3_EL0 and PMOVSR[3] are not reset on capture.

1

PMEVCNTR3_EL0 and PMOVSR[3] are reset on capture.

[2]RP2

Reset performance counter 2. Indicates whether PMEVCNTR2_EL0 and PMOVSR[2] are reset after a capture:

0

PMEVCNTR2_EL0 and PMOVSR[2] are not reset on capture.

1

PMEVCNTR2_EL0 and PMOVSR[2] are reset on capture.

[1]RP1

Reset performance counter 1. Indicates whether PMEVCNTR1_EL0 and PMOVSR[1] are reset after a capture:

0

PMEVCNTR1_EL0 and PMOVSR[1] are not reset on capture.

1

PMEVCNTR1_EL0 and PMOVSR[1] are reset on capture.

[0]RP0

Reset performance counter 0. Indicates whether PMEVCNTR0_EL0 and PMOVSR[0] are reset after a capture:

0

PMEVCNTR0_EL0 and PMOVSR[0] are not reset on capture.

1

PMEVCNTR0_EL0 and PMOVSR[0] are reset on capture.


The PMSRR can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x6F4.

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