ARM Cortex-A57 MPCore Processor Technical Reference ManualRevision: r1p1
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13.7.3. Trace Event Control 0 Register

The TRCEVENTCTL0R characteristics are:

Purpose

Controls the tracing of arbitrary events. Each of the event fields in this register is an event selector.

If any of the selected events occur and the corresponding bit in TRCEVENTCTL1R.INSTEN is 1, then an event element is generated in the instruction trace stream.

If any of the selected events occur and the corresponding bit in TRCEVENTCTL1R.DATAEN is 1, then an event element is generated in the data trace stream.

Usage constraints

Only accepts writes when the trace unit is disabled.

Configurations

Available in all configurations.

Attributes

A 32-bit RW trace register.

See the register summary in Table 13.3.

Figure 13.4 shows the TRCEVENTCTL0R bit assignments.

Figure 13.4. TRCEVENTCL0R bit assignments

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Table 13.6 shows the TRCEVENTCTL0R bit assignments.

Table 13.6. TRCEVENTCL0R bit assignments

BitsNameFunction
[31:24]Event3Identifies the fourth event to trace
[23:16]Event2Identifies the third event to trace
[15:8]Event1Identifies the second event to trace
[7:0]Event0Identifies the first event to trace

The TRCEVENTCTL0R can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x020.

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