13.7.6. Trace Cycle Count Control Register

The TRCCCCTLR characteristics are:


Sets the threshold value for cycle counting.

Usage constraints

Only accepts writes when the trace unit is disabled.

This register must be programmed if TRCCONFIGR.CCI is set to 1. See Trace Configuration Register for more information.


Available in all configurations.


A 32-bit RW trace register.

See the register summary in Table 13.3.

Figure 13.7 shows the TRCCCCTLR bit assignments.

Figure 13.7. TRCCCCTLR bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

Table 13.9 shows the TRCCCCTLR bit assignments.

Table 13.9. TRCCCCTLR bit assignments

[31:12]-Reserved, res0.

Sets the threshold value for instruction trace cycle counting.

The TRCCCCTLR can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x038.

Copyright © 2013, 2014 ARM. All rights reserved.ARM DDI 0488D