13.7.34. Trace Integration Mode Control register

The TRCITCTRL characteristics are:


Controls whether the trace unit is in integration mode.

Usage constraints
  • Accessible only from the memory-mapped interface or from an external agent such as a debugger.

  • If the IME bit changes from one to zero then ARM recommends that the trace unit is reset. Otherwise the trace unit might generate incorrect or corrupt trace and the trace unit resources might behave unexpectedly.


Available in all configurations.


A 32-bit RW management register. The register is reset to zero.

See the register summary in Table 13.3.

Figure 13.35 shows the TRCITCTRL bit assignments.

Figure 13.35. TRCITCTRL bit assignments

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Table 13.37 shows the TRCITCTRL bit assignments.

Table 13.37. TRCITCTRL bit assignments


Reserved, res0


Integration mode enable bit. The possible values are:


The trace unit is not in integration mode.


The trace unit is in integration mode. This mode enables:

  • A debug agent to perform topology detection.

  • SoC test software to perform integration testing.

The TRCITCTRL can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xF00.

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