13.7.2. Trace Auxiliary Control Register

The TRCAUXCTLR characteristics are:

Purpose

The function of this register is to provide implementation defined configuration and control options.

Usage constraints

There are no usage constraints.

Configurations

Available in all configurations.

Attributes

A 32-bit RW trace register. This register is set to zero on a trace unit reset. Resetting this register to zero ensures that none of the features are enabled by default, and that the trace unit resets to a known state.

See the register summary in Table 13.3.

Figure 13.3 shows the TRCAUXCTLR bit assignments.

Figure 13.3. TRCAUXCTLR bit assignments

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Table 13.5 shows the TRCAUXCTLR bit assignments.

Table 13.5. TRCAUXCTLR bit assignments

BitsNameFunction
[31:9]-Reserved, res0.
[8]DBGFLUSHOVERRIDE

Override ETM flush behavior on Debug state entry. The possible values are:

0

ETM FIFO is flushed when the processor enters Debug state.

1

ETM FIFO is not flushed when the processor enters Debug state. This trace unit behavior deviates from the architecturally-specified behavior.

[7]CIFOVERRIDE

Override core interface register repeater clock enable. The possible values are:

0

Core interface is clock gated when DBGEN or NIDEN is LOW.

1

Core interface is not clock gated when DBGEN or NIDEN is LOW.

[6]CLKENOVERRIDE

Override ETM clock enable. The possible values are:

0

ETM clock gating is enabled.

1

ETM clock gating is disabled.

[5]FLUSHOVERRIDE

Override ETM flush behavior. The possible values are:

0

ETM FIFO is flushed and ETM enters idle state when DBGEN or NIDEN is LOW.

1

ETM FIFO is not flushed and ETM does not enter idle state when DBGEN or NIDEN is LOW.

When this bit is set to 1, the trace unit behavior deviates from architecturally-specified behavior.

[4]TSIOVERRIDE

Override TS packet insertion behavior. The possible values are:

0

Timestamp packets are inserted into FIFO when trace activity is LOW.

1

Timestamp packets are inserted into FIFO irrespective of trace activity.

[3]SYNCIOVERRIDE

Override SYNC packet insertion behavior. The possible values are:

0

SYNC packets are inserted into FIFO when trace activity is LOW.

1

SYNC packets are inserted into FIFO irrespective of trace activity.

[2]FRCSYNCOVERFLOW

Force overflows to output synchronization packets. The possible values are:

0

No FIFO overflow when SYNC packets are delayed.

1

Forces FIFO overflow when SYNC packets are delayed.

When this bit is set to 1, the trace unit behavior deviates from architecturally-specified behavior.

[1]IDLEACKOVERRIDE

Force ETM idle acknowledge. The possible values are:

0

ETM idle acknowledge is asserted only when ETM is in idle state.

1

ETM idle acknowledge is asserted irrespective of ETM idle state

When this bit is set to 1, trace unit behavior deviates from architecturally-specified behavior.

[0]AFREADYOVERRIDE

Force assertion of AFREADYM output. The possible values are:

0

ETM AFREADYM output is asserted only when ETM is in idle state or when all the trace bytes in FIFO before a flush request are output.

1

ETM AFREADYM output is always asserted HIGH. When this bit is set to 1, trace unit behavior deviates from architecturally-specified behavior.


The TRCAUXCTLR can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x018.

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