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The TRCVICTLR characteristics are:
Controls instruction trace filtering.
Only accepts writes when the trace unit is disabled.
Only returns stable data when TRCSTATR.PMSTABLE is set to 1.
Must be programmed to set the value of the SSSTATUS bit, that sets the state of the start and stop logic.
Available in all configurations.
A 32-bit RW trace register.
See the register summary in Table 13.3.
Figure 13.9 shows the TRCVICTLR bit assignments.
Table 13.11 shows the TRCVICTLR bit assignments.
Table 13.11. TRCVICTLR bit assignments
Bits | Name | Function |
---|---|---|
[31:24] | - | Reserved, res0. |
[23:20] | EXLEVEL_NS | Each bit controls whether instruction tracing in Non-secure state is enabled for the corresponding Exception level. The bit to Exception level mapping is:
For
example, the value |
[19:16] | EXLEVEL_S | Each bit controls whether instruction tracing in Secure state is enabled for the corresponding Exception level. The bit to Exception level mapping is:
For
example, the value |
[15:12] | - | Reserved, res0. |
[11] | TRCERR | Controls whether a trace unit must trace a System Error exception:
|
[10] | TRCRESET | Controls whether a trace unit must trace a reset exception:
|
[9] | SSSTATUS | Returns the status of the start and stop logic. The possible values are:
The bit only returns stable data when TRCSTATR.PMSTABLE is set to 1. Before software enables the trace unit and TRCPRGCTLR.EN is set to 1, it must write to this bit to set the initial state of the start and stop logic. If the start and stop logic is not used then set this bit to 1. ARM recommends that the value of this bit is set before each trace run begins. |
[8] | - | Reserved, res0. |
[7:0] | EVENT | Event selector. |
The TRCVICTLR can be accessed through the internal memory-mapped
interface and the external debug interface, offset 0x080
.