ARM Cortex-A57 MPCore Processor Technical Reference Manual: 13.7.8. ViewInst Main Control Register

13.7.8. ViewInst Main Control Register

The TRCVICTLR characteristics are:

Purpose

Controls instruction trace filtering.

Usage constraints

Only accepts writes when the trace unit is disabled.
Only returns stable data when TRCSTATR.PMSTABLE is set to 1.
Must be programmed to set the value of the SSSTATUS bit, that sets the state of the start and stop logic.

Configurations

Available in all configurations.

Attributes

A 32-bit RW trace register.

See the register summary in Table 13.3.

Figure 13.9 shows the TRCVICTLR bit assignments.

Figure 13.9. TRCVICTLR bit assignments

Table 13.11 shows the TRCVICTLR bit assignments.

Table 13.11. TRCVICTLR bit assignments

Bits	Name	Function
[31:24]	-	Reserved, res0.
[23:20]	EXLEVEL_NS	Each bit controls whether instruction tracing in Non-secure state is enabled for the corresponding Exception level. The bit to Exception level mapping is: Bit[20] Exception level 0. Bit[21] Exception level 1. Bit[22] Exception level 2. Bit[23] res0. For example, the value `0b0111` enables instruction tracing in Non-secure state for EL0, EL1, and EL2.
[19:16]	EXLEVEL_S	Each bit controls whether instruction tracing in Secure state is enabled for the corresponding Exception level. The bit to Exception level mapping is: Bit[16] Exception level 0. Bit[17] Exception level 1. Bit[18] res0. Bit[19] Exception level 3. For example, the value `0b1011` enables instruction tracing in Secure state for EL0, EL1, and EL3.
[15:12]	-	Reserved, res0.
[11]	TRCERR	Controls whether a trace unit must trace a System Error exception: 0 The trace unit does not trace a System Error exception unless it traces the exception or instruction immediately prior to the System Error exception. 1 The trace unit always traces a System Error exception.
[10]	TRCRESET	Controls whether a trace unit must trace a reset exception: 0 The trace unit does not trace a reset exception unless it traces the exception or instruction immediately prior to the reset exception. 1 The trace unit always traces a reset exception.
[9]	SSSTATUS	Returns the status of the start and stop logic. The possible values are: 0 The start and stop logic is in the stopped state. 1 The start and stop logic is in the started state. The bit only returns stable data when TRCSTATR.PMSTABLE is set to 1. Before software enables the trace unit and TRCPRGCTLR.EN is set to 1, it must write to this bit to set the initial state of the start and stop logic. If the start and stop logic is not used then set this bit to 1. ARM recommends that the value of this bit is set before each trace run begins.
[8]	-	Reserved, res0.
[7:0]	EVENT	Event selector.

The TRCVICTLR can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x080.

Copyright © 2013, 2014 ARM. All rights reserved.	ARM DDI 0488D
Non-Confidential	ID012914
PDF version