1.8. Product revisions

This section describes the differences in functionality between product revisions.

r0p0

First release.

r0p1

The following changes have been made in this release:

  • Updated the reset value of MIDR_EL1, TRCIDR1, and Peripheral ID2 Registers.

  • Added CPUACTLR_EL1.[39] to disable instruction merging.

r1p0

The following changes have been made in this release

  • Updated the reset value of MIDR_EL1, TRCIDR1, and Peripheral ID2 Registers.

  • Added the L2 FEQ 20-entry implementation option.

  • Added L2 Inclusion PF RAM.

  • Added the DBGL1RSTDISABLE input signal.

r1p1

The following changes have been made in this release

  • Updated the reset value of MIDR_EL1.

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