5.1. About the MMU

The Cortex-A57 MPCore multiprocessor is an ARMv8 compliant processor that supports execution in both the AArch64 and AArch32 states. In AArch32 state, the ARMv8 address translation system resembles the ARMv7 address translation system with LPAE and Virtualization Extensions. In AArch64 state, the ARMv8 address translation system resembles an extension to the Long Descriptor Format address translation system to support the expanded virtual and physical address spaces. For more information regarding the address translation formats, see the ARM® Architecture Reference Manual ARMv8. Key differences between the AArch64 and AArch32 address translation systems are that the AArch64 state provides the ability to:

The maximum supported physical address size is:

The MMU controls table walk hardware that accesses translation tables in memory. The MMU works with the L1 and L2 memory system to translate a Virtual Address (VA) to a Physical Address (PA). The MMU enables fine-grained memory system control through a set of virtual-to-physical address mappings and memory attributes held in the L1 and L2 Translation Look-aside Buffers (TLBs).

The MMU has the following features:

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