1.5. Implementation options

Table 1.1 lists the options that the implementer can choose when they implement the Cortex-A57 MPCore multiprocessor in an SoC.

Table 1.1. Cortex-A57 MPCore multiprocessor implementation options

FeatureRange of options
Number of processors1-4
Cryptography engineIncluded or Not
L2 cache size512KB, 1MB, or 2MB
L2 Tag RAM register slice0 or 1
L2 Data RAM register slice0, 1, or 2
L2 arbitration register slice0 or 1
L2 FEQ size[a]0=16 entries, 1=20 entries
Regional gated clock [b]Included or Not
ECC or parity supportSupported in L1 and L2, or L2 only
Bus interfaceACE or CHI

[a] This implementation option is available only in r1p0 and later revisions.

[b] See Regional clock gating for more information.


Note

  • All the processors share an integrated L2 cache and GIC CPU interface. Each processor has the same configuration for the Cryptography engine and L1 ECC or parity.

  • The optional Cryptography engine is not included in the base product of the Cortex-A57 MPCore multiprocessor. ARM requires licensees to have contractual rights to obtain the Cortex-A57 MPCore multiprocessor Cryptography engine.

  • The L2 Tag RAM register slice option adds register slices to the L2 Tag RAMs. The L2 Data RAM register slice option adds register slices to the L2 Data RAMs. Table 1.2 lists valid combinations of the L2 Tag RAM and L2 Data RAM register slice options.

    Table 1.2. Valid combinations of L2 Tag and Data RAM register slice

    L2 Tag RAM register sliceL2 Data RAM register slice
    00
    01
    02
    11
    12

  • If the L2 arbitration register slice is included then it adds an additional pipeline stage in the processor-L2 arbitration logic interface.

  • The Cortex-A57 MPCore multiprocessor must be configured with a CHI interface to connect to a CHI interconnect.

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