5.3. TLB match process

The ARMv8 architecture provides for multiple VA spaces that are translated differently. The TLB entries store all the required context information to facilitate a match and avoid the requirement for a TLB flush on a context or virtual machine switch. Each TLB entry contains a VA, page size, PA, and a set of memory properties that include the memory type and access permissions. Each entry is associated with a particular ASID, or as global for all application spaces. The TLB entry also contains a field to store the VMID in the entry, applicable to accesses made from the Non-secure state. There is also a memory space identifier that records whether the request occurred at the EL3 Exception level, Non-secure EL2 Exception level, or Secure and Non-secure EL0 or EL1 Exception levels. A TLB entry match occurs when the following conditions are met:


  • For a request originating from EL2 or EL3, the ASID and VMID match are ignored.

  • For a request originating from Secure state, the VMID match is ignored.

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