13.7.20. Trace ID Register 3

The TRCIDR3 characteristics are:

Purpose

Indicates:

  • Whether TRCVICTLR is supported.

  • The number of processors available for tracing.

  • If an Exception level supports instruction tracing.

  • The minimum threshold value for instruction trace cycle counting.

  • Whether the synchronization period is fixed.

  • Whether TRCSTALLCTLR is supported and if so whether it supports trace overflow prevention and supports stall control of the processor.

Usage constraints

There are no usage constraints.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 13.3.

Figure 13.21 shows the TRCIDR3 bit assignments.

Figure 13.21. TRCIDR3 bit assignments

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Table 13.23 shows the TRCIDR3 bit assignments.

Table 13.23. TRCIDR3 bit assignments

BitsNameFunction
[31]NOOVERFLOW

Indicates whether TRCSTALLCTLR.NOOVERFLOW is supported. This value is:

0

TRCSTALLCTLR.NOOVERFLOW is not supported. STALLCTL is 0.

[30:28]NUMPROC

Indicates the number of processors available for tracing. This value is:

0b000

The trace unit can trace one processor.

[27]SYSSTALL

Indicates whether stall control is supported. This value is:

0

The system does not support stall control of the processor.

[26]STALLCTL

Indicates whether TRCSTALLCTLR is supported. This value is:

0

TRCSTALLCTLR is not supported.

[25]SYNCPR

Indicates whether there is a fixed synchronization period. This value is:

0

TRCSYNCPR is read-write so software can change the synchronization period.

[24]TRCERR

Indicates whether TRCVICTLR.TRCERR is supported. This value is:

1

TRCVICTLR.TRCERR is supported.

[23:20]EXLEVEL_NS

Each bit controls whether instruction tracing in Non-secure state is supported for the corresponding Exception level. The value is:

0b0111

Instruction tracing in Non-secure state is supported for EL0, EL1, and EL2.

Note

The bit to Exception level mapping is:

Bit[20]

Exception level 0.

Bit[21]

Exception level 1.

Bit[22]

Exception level 2.

Bit[23]

Always res0.

[19:16]EXLEVEL_S

Each bit controls whether instruction tracing in Secure state is supported for the corresponding Exception level. The value is:

0b1011

Instruction tracing in Secure state is supported for EL0, EL1, and EL3.

Note

The bit to Exception level mapping is:

Bit[16]

Exception level 0.

Bit[15]

Exception level 1.

Bit[14]

Always res0.

Bit[13]

Exception level 3.

[15:12]-

Reserved, res0.

[11:0]CCITMIN

The minimum value that can be programmed in TRCCCCTLR.THRESHOLD. This value is:

0x100

Minimum value for cycle counting in the instruction trace.


The TRCIDR3 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x1EC.

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