12.6.11. CTI Peripheral Identification Registers

The Peripheral Identification Registers provide standard information required for all components that conform to the ARM CoreSight architecture. There is a set of eight registers, listed in register number order in Table 12.16.

Table 12.16. Summary of the CTI Peripheral Identification Registers

RegisterValueOffset
CTIPIDR40x040xFD0
CTIPIDR50x000xFD4
CTIPIDR60x000xFD8
CTIPIDR70x000xFDC
CTIPIDR00x060xFE0
CTIPIDR10xB90xFE4
CTIPIDR20x4B0xFE8
CTIPIDR30x000xFEC

Only bits[7:0] of each CTI Peripheral ID Register are used, with bits[31:8] reserved. Together, the eight CTI Peripheral ID Registers define a single 64-bit Peripheral ID.

The CTI Peripheral ID registers are:

CTI Peripheral Identification Register 0

The CTIPIDR0 characteristics are:

Purpose

Provides information to identify a CTI component.

Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

OffDLKOSLKEPMADSLKDefault
----RORO

Table 12.4 describes the access conditions.

Configurations

CTIPIDR0 is in the Debug power domain.

Attributes

See the register summary in Table 12.3.

Figure 12.12 shows the CTIPIDR0 bit assignments.

Figure 12.12. CTIPIDR0 bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 12.17 shows the CTIPIDR0 bit assignments.

Table 12.17. CTIPIDR0 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0

[7:0]Part_0
0x06

Least significant byte of the cross trigger part number


CTI Peripheral Identification Register 1

The CTIPIDR1 characteristics are:

Purpose

Provides information to identify a CTI component.

Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

OffDLKOSLKEPMADSLKDefault
----RORO

Table 12.4 describes the access conditions.

Configurations

CTIPIDR1 is in the Debug power domain.

Attributes

See the register summary in Table 12.3.

Figure 12.13 shows the CTIPIDR1 bit assignments.

Figure 12.13. CTIPIDR1 bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 12.18 shows the CTIPIDR1 bit assignments.

Table 12.18. CTIPIDR1 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0.

[7:4]DES_0
0xB

ARM Limited. This is the least significant nibble of JEP106 ID code.

[3:0]Part_1
0x9

Most significant nibble of the cross trigger interface part number.


CTI Peripheral Identification Register 2

The CTIPIDR2 characteristics are:

Purpose

Provides information to identify a CTI component.

Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

OffDLKOSLKEPMADSLKDefault
----RORO

Table 12.4 describes the access conditions.

Configurations

CTIPIDR2 is in the Debug power domain.

Attributes

See the register summary in Table 12.3.

Figure 12.14 shows the CTIPIDR2 bit assignments.

Figure 12.14. CTIPIDR2 bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 12.19 shows the CTIPIDR2 bit assignments.

Table 12.19. CTI PIDR2 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0.

[7:4]Revision
0x4

Part major revision.

[3]JEDEC
0b1

res1. Indicates a JEP106 identity code is used.

[2:0]DES_1
0b011

ARM Limited. This is the most significant nibble of JEP106 ID code.


CTI Peripheral Identification Register 3

The CTIPIDR3 characteristics are:

Purpose

Provides information to identify a CTI component.

Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

OffDLKOSLKEPMADSLKDefault
----RORO

Table 12.4 describes the access conditions.

Configurations

CTIPIDR3 is in the Debug power domain.

Attributes

See the register summary in Table 12.3.

Figure 12.15 shows the CTIPIDR3 bit assignments.

Figure 12.15. CTIPIDR3 bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 12.20 shows the CTIPIDR3 bit assignments.

Table 12.20. CTIPIDR3 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0

[7:4]REVAND
0x0

Part minor revision

[3:0]CMOD
0x0

Customer modified


CTI Peripheral Identification Register 4

The CTIPIDR4 characteristics are:

Purpose

Provides information to identify a CTI component.

Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

OffDLKOSLKEPMADSLKDefault
----RORO

Table 12.4 describes the access conditions.

Configurations

CTIPIDR4 is in the Debug power domain.

Attributes

See the register summary in Table 12.3.

Figure 12.16 shows the CTIPIDR4 bit assignments.

Figure 12.16. CTIPIDR4 bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 12.21 shows the CTIPIDR4 bit assignments.

Table 12.21. CTIPIDR4 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0.

[7:4]Size
0x0

Size of the component. Log2 the number of 4KB pages from the start of the component to the end of the CTI Component ID registers.

[3:0]DES_2
0x4

ARM Limited. This is the least significant nibble JEP106 continuation code.


CTI Peripheral Identification Register 5-7

No information is held in the Peripheral ID5, Peripheral ID6, and Peripheral ID7 Registers. They are reserved for future use and are res0.

Copyright © 2013, 2014 ARM. All rights reserved.ARM DDI 0488D
Non-ConfidentialID012914