12.6.12. CTI Component Identification Registers

There are four read-only CTI Component Identification Registers, Component ID0 through Component ID3. Table 12.22 shows these registers.

Table 12.22. Summary of the CTI Component Identification Registers

RegisterValueOffset
CTICIDR00x0D0xFF0
CTICIDR10x900xFF4
CTICIDR20x050xFF8
CTICIDR30xB10xFFC

The CTI Component ID registers are:

CTI Component Identification Register 0

The CTICIDR0 characteristics are:

Purpose

Provides information to identify a CTI component.

Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

OffDLKOSLKEPMADSLKDefault
----RORO

Table 12.4 describes the access conditions.

Configurations

CTICIDR0 is in the Debug power domain.

Attributes

See the register summary in Table 12.3.

Figure 12.17 shows the CTICIDR0 bit assignments.

Figure 12.17. CTICIDR0 bit assignments

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Table 12.23 shows the CTICIDR0 bit assignments.

Table 12.23. CTICIDR0 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0

[7:0]PRMBL_0
0x0D

Preamble byte 0


CTI Component Identification Register 1

The CTICIDR1 characteristics are:

Purpose

Provides information to identify a CTI component.

Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

OffDLKOSLKEPMADSLKDefault
----RORO

Table 12.4 describes the access conditions.

Configurations

CTICIDR1 is in the Debug power domain.

Attributes

See the register summary in Table 12.3.

Figure 12.18 shows the CTICIDR1 bit assignments.

Figure 12.18. CTICIDR1 bit assignments

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Table 12.24 shows the CTICIDR1 bit assignments.

Table 12.24. CTICIDR1 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0

[7:4]CLASS
0x9

Debug component

[3:0]PRMBL_1
0x0

Preamble


CTI Component Identification Register 2

The CTICIDR2 characteristics are:

Purpose

Provides information to identify a CTI component.

Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

OffDLKOSLKEPMADSLKDefault
----RORO

Table 12.4 describes the access conditions.

Configurations

CTICIDR2 is in the Debug power domain.

Attributes

See the register summary in Table 12.3.

Figure 12.19 shows the CTICIDR2 bit assignments.

Figure 12.19. CTICIDR2 bit assignments

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Table 12.25 shows the CTICIDR2 bit assignments.

Table 12.25. CTICIDR2 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0

[7:0]PRMBL_2
0x05

Preamble byte 2


CTI Component Identification Register 3

The CTICIDR3 characteristics are:

Purpose

Provides information to identify a CTI component.

Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

OffDLKOSLKEPMADSLKDefault
----RORO

Table 12.4 describes the access conditions.

Configurations

CTICIDR3 is in the Debug power domain.

Attributes

See the register summary in Table 12.3.

Figure 12.20 shows the CTICIDR3 bit assignments.

Figure 12.20. CTICIDR3 bit assignments

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Table 12.26 shows the CTICIDR3 bit assignments.

Table 12.26. CTICIDR3 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0

[7:0]PRMBL_3
0xB1

Preamble byte 3


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