10.7. Memory-mapped register summary

Table 10.10 shows the offset address for the registers that are accessible from the internal memory-mapped interface or the external debug interface.

Table 10.10. Memory-mapped debug register summary

OffsetNameTypeWidthDescription
0x000-0x01C---Reserved
0x020EDESRRW32-bitExternal Debug Event Status Register [a]
0x024EDECRRW32-bitExternal Debug Execution Control Register [a]
0x028-0x02C---Reserved
0x030EDWARloRO32-bitExternal Debug Watchpoint Address Register, low word [a]
0x034EDWARhiRO32-bitExternal Debug Watchpoint Address Register, high word [a]
0x038-0x07C---Reserved
0x080DBGDTRRX_EL0RW32-bitDebug Data Transfer Register, Receive [a]
0x084EDITRWO32-bitExternal Debug Instruction Transfer Register [a]
0x088EDSCRRW32-bit

External Debug Status and Control Register [a]

0x08CDBGDTRTX_EL0RW32-bitDebug Data Transfer Register, Transmit [a]
0x090EDRCRWO32-bitExternal Debug Reserve Control Register
0x094EDACRRW32-bitExternal Debug Auxiliary Control Register
0x098EDECCRRW32-bitExternal Debug Exception Catch Control Register [a]
0x09C---Reserved
0x0A0EDPCSRloRO32-bit

External Debug Program Counter Sample Register, low word [a]

0x0A4EDCIDSRRO32-bitExternal Debug Context ID Sample Register [a]
0x0A8EDVIDSRRO32-bitExternal Debug Virtual Context Sample Register [a]
0x0ACEDPCSRhiRO32-bit

External Debug Program Counter Sample Register, high word [a]

0x0B0-0x2FC---Reserved
0x300OSLAR_EL1WO32-bitDebug OS Lock Access Register [a]
0x304-0x30C---Reserved
0x310EDPRCRRW32-bitExternal Debug Power/Reset Control Register [a]
0x314EDPRSRRO32-bit

External Debug Processor Status Register [a]

0x318-0x3FC---Reserved
0x400DBGBVR0_EL1[31:0]RW32-bitDebug Breakpoint Value Register 0 [a]
0x404DBGBVR0_EL1[63:32]
0x408DBGBCR0_EL1RW32-bitDebug Breakpoint Control Registers, EL1
0x40C---Reserved
0x410DBGBVR1_EL1[31:0]RW32-bitDebug Breakpoint Value Register 1 [a]
0x414DBGBVR1_EL1[63:32]
0x418DBGBCR1_EL1RW32-bitDebug Breakpoint Control Registers, EL1
0x41C---Reserved
0x420DBGBVR2_EL1[31:0]RW32-bitDebug Breakpoint Value Register 2 [a]
0x424DBGBVR2_EL1[63:32]
0x428DBGBCR2_EL1RW32-bitDebug Breakpoint Control Registers, EL1
0x42C---Reserved
0x430DBGBVR3_EL1[31:0]RW32-bitDebug Breakpoint Value Register 3 [a]
0x434DBGBVR3_EL1[63:32]
0x438DBGBCR3_EL1RW32-bitDebug Breakpoint Control Registers, EL1
0x43C---Reserved
0x440DBGBVR4_EL1[31:0]RW32-bitDebug Breakpoint Value Register 4 [a]
0x444DBGBVR4_EL1[63:32]
0x448DBGBCR4_EL1RW32-bitDebug Breakpoint Control Registers, EL1
0x44C---Reserved
0x450DBGBVR5_EL1[31:0]RW32-bitDebug Breakpoint Value Register 5 [a]
0x454DBGBVR5_EL1[63:32]
0x458DBGBCR5_EL1RW32-bitDebug Breakpoint Control Registers, EL1
0x45C-0x7FC---Reserved
0x800DBGWVR0_EL1[31:0]RW32-bitDebug Watchpoint Value Register 0 [a]
0x804DBGWVR0_EL1[63:32]
0x808DBGWCR0_EL1RW32-bitDebug Watchpoint Control Registers, EL1
0x80C---Reserved
0x810DBGWVR1_EL1[31:0]RW32-bitDebug Watchpoint Value Register 1 [a]
0x814DBGWVR1_EL1[63:32]
0x818DBGWCR1_EL1RW32-bitDebug Watchpoint Control Registers, EL1
0x81C---Reserved
0x820DBGWVR2_EL1[31:0]RW32-bitDebug Watchpoint Value Register 2 [a]
0x824DBGWVR2_EL1[63:32]
0x828DBGWCR2_EL1RW32-bitDebug Watchpoint Control Registers, EL1
0x82C---Reserved
0x830DBGWVR3_EL1[31:0]RW32-bitDebug Watchpoint Value Register 3 [a]
0x834DBGWVR3_EL1[63:32]
0x838DBGWCR3_EL1RW32-bitDebug Watchpoint Control Registers, EL1
0x83C-0xCFC---Reserved
0xD00MIDR_EL1RO32-bitMain ID Register, EL1
0xD04-0xD1C---Reserved
0xD20ID_AA64PFR0_EL1[31:0]RO32-bitAArch64 Processor Feature Register 0, EL1
0xD24ID_AA64PFR0_EL1[63:32]RO32-bit
0xD28ID_AA64DFR0_EL1[31:0]RO32-bitAArch64 Debug Feature Register 0, EL1
0xD2CID_AA64DFR0_EL1[63:32]RO32-bit
0xD30ID_AA64ISAR0_EL1[31:0]RO32-bitAArch64 Instruction Set Attribute Register 0, EL1
0xD34ID_AA64ISAR0_EL1[63:32]RO32-bit
0xD38ID_AA64MMFR0_EL1[31:0]RO32-bitAArch64 Memory Model Feature Register 0, EL1
0xD3CID_AA64MMFR0_EL1[63:32]RO32-bit
0xD40ID_AA64PFR1_EL1[31:0]RO32-bitAArch64 Processor Feature Register 1 low word, res0
0xD44ID_AA64PFR1_EL1[63:32]RO32-bitAArch64 Processor Feature Register 1 high word, res0
0xD48ID_AA64DFR1_EL1[31:0]RO32-bitAArch64 Debug Feature Register 1 low word, res0
0xD4CID_AA64DFR1_EL1[63:32]RO32-bitAArch64 Debug Feature Register 1 high word, res0
0xD50ID_AA64ISAR1_EL1[31:0]RO32-bitAArch64 Instruction Set Attribute Register 1 low word, res0
0xD54ID_AA64ISAR1_EL1[63:32]RO32-bitAArch64 Instruction Set Attribute Register 1 high word, res0
0xD58ID_AA64MMFR1_EL1[31:0]RO32-bitAArch64 Memory Model Feature Register 1 low word, res0
0xD5CID_AA64MMFR1_EL1[63:32]RO32-bitAArch64 Memory Model Feature Register 1 high word, res0
0xD60-0xEF4---Reserved
0xEF8EDITOCTRLWO32-bitExternal Debug Integration Output Control Register
0xEFCEDITISRRO32-bitExternal Debug Integration Input Status Register
0xF00EDITCTRLRW32-bitExternal Debug Integration Mode Control Register
0xF04-0xF9C---Reserved
0xFA0DBGCLAIMSET_EL1RW32-bitDebug Claim Tag Set Register [a]
0xFA4DBGCLAIMCLR_EL1RW32-bitDebug Claim Tag Clear Register [a]
0xFA8EDDEVAFF0RO32-bitExternal Debug Device Affinity Register 0. See Multiprocessor Affinity Register, EL1
0xFACEDDEVAFF1RO32-bitExternal Debug Device Affinity Register 1, res0
0xFB0EDLARWO32-bit

External Debug Lock Access Register [a]

0xFB4EDLSRRO32-bitExternal Debug Lock Status Register [a]
0xFB8DBGAUTHSTATUS_EL1RO32-bit

Debug Authentication Status Register [a]

0xFBCEDDEVARCHRO32-bitExternal Debug Device Architecture Register [a]
0xFC0EDDEVID2RO32-bitExternal Debug Device ID Register 2, res0
0xFC4EDDEVID1RO32-bitExternal Debug Device ID Register 1
0xFC8EDDEVIDRO32-bitExternal Debug Device ID Register 0
0xFCCEDDEVTYPERO32-bit

External Debug Device Type Register [a]

0xFD0EDPIDR4RO32-bitDebug Peripheral Identification Register 4
0xFD4-0xFDCEDPIDR5-7RO32-bitDebug Peripheral Identification Register 5-7
0xFE0EDPIDR0RO32-bitDebug Peripheral Identification Register 0
0xFE4EDPIDR1RO32-bitDebug Peripheral Identification Register 1
0xFE8EDPIDR2RO32-bitDebug Peripheral Identification Register 2
0xFECEDPIDR3RO32-bitDebug Peripheral Identification Register 3
0xFF0EDCIDR0RO32-bitDebug Component Identification Register 0
0xFF4EDCIDR1RO32-bitDebug Component Identification Register 1
0xFF8EDCIDR2RO32-bitDebug Component Identification Register 2
0xFFCEDCIDR3RO32-bitDebug Component Identification Register 3

[a] See the ARM® Architecture Reference Manual ARMv8 for more information.


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