10.2.4. External access permissions

External access permission to the debug registers is subject to the conditions at the time of the access. Table 10.1 describe the processor response to accesses through the external debug interface.

Table 10.1. External register access conditions

ConditionCondition triggerDescription
OffEDPRSR.PU is 0

Core power domain is completely off, or in a low-power state where the Core power domain registers cannot be accessed.

Note

If debug power is off then all external debug and memory-mapped register accesses return an error.

DLKEDPRSR.DLK is 1OS Double Lock is locked.
OSLKOSLSR_EL1.OSLK is 1OS Lock is locked.
EDADAllowExternalDebugAccess() ==FALSEExternal debug access disabled. When an error is returned because of the EDAD condition, and this is the highest priority error condition, EDPRSR.SDAD is set to 1. Otherwise SDAD is unchanged.
SLKMemory-mapped interface onlySoftware Lock is locked. For the external debug interface, ignore this condition.
Default-None of the conditions apply, normal access.

Table 10.2 shows an example of external register access conditions for access to a Performance Monitors register. To determine the access permission for the register, scan the columns from left to right. Stop at the first column whose condition is true, the entry gives the access permission of the register and scanning stops.

Table 10.2. External register access conditions example

OffDLKOSLKEDADSLKDefault
----RO/WIRO

Copyright © 2013, 2014 ARM. All rights reserved.ARM DDI 0488D
Non-ConfidentialID012914