10.3. AArch64 debug register summary

Table 10.3 shows the debug control registers that are accessible in AArch64 state. These registers are accessed by the MRS and MSR instructions.

Table 10.3 also shows the offset address for the AArch64 registers that are accessible from the internal memory-mapped interface or the external debug interface. See the Memory-mapped register summary for a complete list of registers accessible from the internal memory-mapped or the external debug interface.

Table 10.3. AArch64 debug register summary

OffsetNameTypeWidthDescription
-DBGDTR_EL0RW64-bitDebug Data Transfer Register, half-duplex [a]
-DBGVCR32_EL2RW32-bitDebug Vector Catch Register [a]
-MDCCINT_EL1RW32-bitMonitor Debug Comms Channel Interrupt Enable Register [a]
-MDCCSR_EL0RO32-bitMonitor Debug Comms Channel Status Register [a]
-MDRAR_EL1RO64-bitMonitor Debug ROM Address Register [a]
-MDSCR_EL1RW32-bitMonitor Debug System Control Register [a]
-OSDTRRX_EL1RW32-bitOS Lock Data Transfer Register, Receive, External View [a]
-OSDTRTX_EL1RW32-bitOS Lock Data Transfer Register, Transmit, External View [a]
-OSDLR_EL1RW32-bitOS Double Lock Register [a]
-OSLSR_EL1RO32-bitOS Lock Status Register
0x080DBGDTRRX_EL0RO32-bitDebug Data Transfer Register, Receive, Internal View [a]
0x08CDBGDTRTX_EL0WO32-bitDebug Data Transfer Register, Transmit, Internal View [a]
0x098OSECCR_EL1RW32-bitOS Lock Exception Catch Control Register [a]
0x310DBGPRCR_EL1RW32-bitDebug Power/Reset Control Register [a]
0x400DBGBVR0_EL1RW64-bitDebug Breakpoint Value Register 0 [a]
0x408DBGBCR0_EL1RW32-bitDebug Breakpoint Control Registers, EL1
0x410DBGBVR1_EL1RW64-bitDebug Breakpoint Value Register 1 [a]
0x418DBGBCR1_EL1RW32-bitDebug Breakpoint Control Registers, EL1
0x420DBGBVR2_EL1RW64-bitDebug Breakpoint Value Register 2 [a]
0x428DBGBCR2_EL1RW32-bitDebug Breakpoint Control Registers, EL1
0x430DBGBVR3_EL1RW64-bitDebug Breakpoint Value Register 3 [a]
0x438DBGBCR3_EL1RW32-bitDebug Breakpoint Control Registers, EL1
0x440DBGBVR4_EL1RW64-bitDebug Breakpoint Value Register 4 [a]
0x448DBGBCR4_EL1RW32-bitDebug Breakpoint Control Registers, EL1
0x450DBGBVR5_EL1RW64-bitDebug Breakpoint Value Register 5 [a]
0x458DBGBCR5_EL1RW32-bitDebug Breakpoint Control Registers, EL1
0x800DBGWVR0_EL1RW64-bitDebug Watchpoint Value Register 0 [a]
0x808DBGWCR0_EL1RW32-bitDebug Watchpoint Control Registers, EL1
0x810DBGWVR1_EL1RW64-bitDebug Watchpoint Value Register 1 [a]
0x818DBGWCR1_EL1RW32-bitDebug Watchpoint Control Registers, EL1
0x820DBGWVR2_EL1RW64-bitDebug Watchpoint Value Register 2 [a]
0x828DBGWCR2_EL1RW32-bitDebug Watchpoint Control Registers, EL1
0x830DBGWVR3_EL1RW64-bitDebug Watchpoint Value Register 3 [a]
0x838DBGWCR3_EL1RW32-bitDebug Watchpoint Control Registers, EL1
0xFA0DBGCLAIMSET_EL1RW32-bitDebug Claim Tag Set Register [a]
0xFA4DBGCLAIMCLR_EL1RW32-bitDebug Claim Tag Clear Register [a]
0xFB0OSLAR_EL1WO32-bitDebug OS Lock Access Register [a]
0xFD8DBGAUTHSTATUS_EL1RO32-bitDebug Authentication Status Register [a]

[a] See the ARM® Architecture Reference Manual ARMv8 for more information.


Copyright © 2013, 2014 ARM. All rights reserved.ARM DDI 0488D
Non-ConfidentialID012914