10.6.1. Debug ID Register

The DBGDIDR characteristics are:

Purpose

Specifies:

  • The version of the Debug architecture that is implemented.

  • Some features of the debug implementation.

Usage constraints

The accessibility to the DBGDIDR by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
RORORORORORO
Configurations

The DBGDIDR is Common to Secure and Non-secure states.

Attributes

See the register summary in Table 10.6.

Figure 10.4 shows the DBGDIDR bit assignments.

Figure 10.4. DBGDIDR bit assignments

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Table 10.7 shows the DBGDIDR bit assignments.

Table 10.7. DBGDIDR bit assignments

BitsNameFunction
[31:28]WRPs

The number of Watchpoint Register Pairs (WRPs) implemented. The number of implemented WRPs is one more than the value of this field. The value is:

0x3

The processor implements 4 WRPs.

This field has the same value as ID_AA64DFR0_EL1.WRPs.

[27:24]BRPs

The number of Breakpoint Register Pairs (BRPs) implemented. The number of implemented BRPs is one more than the value of this field. The value is:

0x5

The processor implements 6 BRPs.

This field has the same value as ID_AA64DFR0_EL1.BRPs.

[23:20]CTX_CMPs

The number of BRPs that can be used for Context matching. This is one more than the value of this field. The value is:

0x1

The processor implements two Context matching breakpoints, breakpoints 4 and 5.

This field has the same value as ID_AA64DFR0_EL1.CTX_CMPs.

[19:16]Version

The Debug architecture version.

0x6

The processor implements ARMv8 Debug architecture.

[15]-

Reserved, res1.

[14]nSUHD_imp

Secure User Halting Debug not implemented bit. The value is:

1

The processor does not implement Secure User Halting Debug.

[13]-Reserved, res0.
[12]SE_imp

Security Extensions implemented bit. The value is:

1

The processor implements Security Extensions.

[11:0]-

Reserved, res0.


To access the DBGDIDR in AArch32 state, read or write the CP14 register with:

MRC p14, 0, <Rt>, c0, c0, 0; Read Debug ID Register
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