10.8.2. External Debug Auxiliary Control Register

The EDACR characteristics are:

Purpose

Provides implementation defined configuration and control options.

Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

OffDLKOSLKEDADSLKDefault
----RORW

Table 10.1 describes the access conditions.

Configurations

The EDACR is in the Debug power domain.

Attributes

See the register summary in Table 10.10.

Figure 10.8 shows the EDACR bit assignments.

Figure 10.8. EDACR bit assignments

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Table 10.12 shows the EDACR bit assignments.

Table 10.12. EDACR bit assignments

BitsNameFunction
[31:4]-

Reserved, res0.

[3]Override idle acknowledgement

Override idle acknowledgement signal to processor. The possible values are:

0

Processor waits for the debug register access logic to go idle before it enters the idle state. This is the reset value.

1

Processor does not wait for the debug register access logic to go idle before it enters the idle state.

[2]Core debug reset status

Read-only status bit that reflects the current reset state of the debug logic in the processor power domain:

0

Debug logic in processor power domain is not in reset state.

1

Debug logic in processor power domain is currently in reset state.

[1]Debug powerdown override

Debug powerdown control bit. If debug is enabled and this bit is:

0

Error response is generated for APB accesses to the processor domain debug registers when the processor is powered down or OS Double Lock is set. This is the reset value.

1

APB accesses to the processor domain debug registers proceed normally when the processor is powered down or OS Double Lock is set.

[0]Debug clock stop control

Debug clock control bit. If debug is enabled and this bit is:

0

Does not prevent the clock generator from stopping the processor clock. This is the reset value.

1

Prevents the clock generator from stopping the processor clock.


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