4.4.3. c2 registers

Table 4.84 shows the System registers when CRn is c2 and the processor is in AArch32 state.

Table 4.84. c2 register summary

op1CRmop2NameTypeResetDescription
0c00TTBR0RWUNKTranslation Table Base Register 0 and Register 1
  1TTBR1RWUNK
  2TTBCRRW0x00000000[a]Translation Table Base Control Register
4c02HTCRRWUNKHyp Translation Control Register
 c12VTCRRWUNKVirtualization Translation Control Register, see the ARM® Architecture Reference Manual ARMv8

[a] The reset value is 0x00000000 for the Secure copy of the register. The reset value for the EAE bit of the Non-secure copy of the register is 0b0. You must program the Non-secure copy of the register with the required initial value, as part of the processor boot sequence.


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