7.1. About the L2 memory system

The L2 memory system consists of a tightly-coupled L2 cache and an integrated Snoop Control Unit (SCU), connecting up to four processors within a Cortex-A57 MPCore device and a configurable coherent external interface supporting AMBA4 (ACE) or CHI architectures. The L2 memory system also interfaces with an Accelerator Coherency Port (ACP) that is implemented as an AXI slave interface.

The features of the L2 memory system include:


  • The Cortex-A57 MPCore multiprocessor does not support TLB or cache lockdown.

  • The L2 FEQ20 implementation option is available only in r1p0 and later revisions.

Copyright © 2013, 2014 ARM. All rights reserved.ARM DDI 0488D