13.7.37. ETM Peripheral Identification Registers

The ETM Peripheral Identification Registers provide standard information required for all CoreSight components. There is a set of eight registers, listed in register number order in Table 13.38.

Table 13.38. Summary of the Trace Peripheral ID Registers

RegisterValueOffset
TRCPIDR40x040xFD0
TRCPIDR50x000xFD4
TRCPIDR60x000xFD8
TRCPIDR70x000xFDC
TRCPIDR00x5E0xFE0
TRCPIDR10xB90xFE4
TRCPIDR20x2B0xFE8
TRCPIDR30x000xFEC

Only bits[7:0] of each Trace Peripheral ID Register are used, with bits[31:8] reserved. Together, the eight Trace Peripheral ID Registers define a single 64-bit Peripheral ID.

The Trace Peripheral ID registers are:

ETM Peripheral Identification Register 0

The TRCPIDR0 characteristics are:

Purpose

Provides information to identify a trace component.

Usage constraints
  • Only bits[7:0] are valid.

  • Accessible only from the memory-mapped interface or the external debugger interface.

Configurations

Available in all implementations.

Attributes

A 32-bit RO management register.

See the register summary in Table 13.3.

Figure 13.36 shows the TRCPIDR0 bit assignments.

Figure 13.36. TRCPIDR0 bit assignments

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Table 13.39 shows the TRCPIDR0 bit assignments.

Table 13.39. TRCPIDR0 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0.

[7:0]Part_0
0x5E

Least significant byte of the ETM part number.


TRCPIDR0 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFE0.

ETM Peripheral Identification Register 1

The TRCPIDR1 characteristics are:

Purpose

Provides information to identify a trace component.

Usage constraints
  • Only bits[7:0] are valid.

  • Accessible only from the memory-mapped interface or the external debugger interface.

Configurations

Available in all implementations.

Attributes

A 32-bit RO management register.

See the register summary in Table 13.3.

Figure 13.37 shows the TRCPIDR1 bit assignments.

Figure 13.37. TRCPIDR1 bit assignments

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Table 13.40 shows the TRCPIDR1 bit assignments.

Table 13.40. TRCPIDR1 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0.

[7:4]DES_0
0xB

ARM Limited. This is the least significant nibble of JEP106 ID code.

[3:0]Part_1
0x9

Most significant nibble of the ETM part number.


TRCPIDR1 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFE4.

ETM Peripheral Identification Register 2

The TRCPIDR2 characteristics are:

Purpose

Provides information to identify a trace component.

Usage constraints
  • Only bits[7:0] are valid.

  • Accessible only from the memory-mapped interface or the external debugger interface.

Configurations

Available in all implementations.

Attributes

A 32-bit RO management register.

See the register summary in Table 13.3.

Figure 13.38 shows the TRCPIDR2 bit assignments.

Figure 13.38. TRCPIDR2 bit assignments

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Table 13.41 shows the TRCPIDR2 bit assignments.

Table 13.41. TRCPIDR2 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0.

[7:4]Revision
0x2

Part major revision.

[3]JEDEC
0b1

res1. Indicates a JEP106 identity code is used.

[2:0]DES_1
0b011

ARM Limited. This is the most significant nibble of JEP106 ID code.


TRCPIDR2 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFE8.

ETM Peripheral Identification Register 3

The TRCPIDR3 characteristics are:

Purpose

Provides information to identify a trace component.

Usage constraints
  • Only bits[7:0] are valid.

  • Accessible only from the memory-mapped interface or the external debugger interface.

Configurations

Available in all implementations.

Attributes

A 32-bit RO management register.

See the register summary in Table 13.3.

Figure 13.39 shows the TRCPIDR3 bit assignments.

Figure 13.39. TRCPIDR3 bit assignments

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Table 13.42 shows the TRCPIDR3 bit assignments.

Table 13.42. TRCPIDR3 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0.

[7:4]REVAND
0x0

Part minor revision.

[3:0]CMOD
0x0

Customer modified.


TRCPIDR3 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFEC.

ETM Peripheral Identification Register 4

The TRCPIDR4 characteristics are:

Purpose

Provides information to identify a trace component.

Usage constraints
  • Only bits[7:0] are valid.

  • Accessible only from the memory-mapped interface or the external debugger interface.

Configurations

Available in all implementations.

Attributes

A 32-bit RO management register.

See the register summary in Table 13.3.

Figure 13.40 shows the TRCPIDR4 bit assignments.

Figure 13.40. TRCPIDR4 bit assignments

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Table 13.43 shows the TRCPIDR4 bit assignments.

Table 13.43. TRCPIDR4 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0.

[7:4]Size
0x0

Size of the component. Log2 the number of 4KB pages from the start of the component to the end of the ETM Component ID registers.

[3:0]DES_2
0x4

ARM Limited. This is the least significant nibble of the JEP106 continuation code.


TRCPIDR4 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFD0.

ETM Peripheral Identification Register 5-7

No information is held in the Peripheral ID5, Peripheral ID6 and Peripheral ID7 Registers. They are reserved for future use and are res0.

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