4.4.10. c9 registers

Table 4.91 shows the System registers when CRn is c9 and the processor is in AArch32 state.

Table 4.91. c9 register summary

op1CRmop2NameTypeResetDescription
0c120PMCRRW0x41013000Performance Monitors Control Register. See Performance Monitors Control Register, EL0.
 1PMCNTENSETRWUNKPerformance Monitors Count Enable Set Register. [a]
 2PMCNTENCLRRWUNKPerformance Monitors Count Enable Clear Register. [a]
 3PMOVSRRWUNKPerformance Monitors Overflow Flag Status Register. [a]
 4PMSWINCWO-Performance Monitors Software Increment Register. [a]
 5PMSELRRWUNKPerformance Monitors Event Counter Selection Register. [a]
 6PMCEID0RO0x7FFF0F3FPerformance Monitors Common Event Identification Register 0. See Performance Monitors Common Event Identification Register 0, EL0.
 7PMCEID1RO0x00000000Performance Monitors Common Event Identification Register 1. [a]
 c130PMCCNTRRWUNKPerformance Monitors Cycle Counter Register. [a]
 1PMXEVTYPERRWUNKPerformance Monitors Selected Event Type Register. [a]
 PMCCFILTRRW0x00000000Performance Monitors Cycle Count Filter Register. [a]
 2PMXEVCNTRRWUNKPerformance Monitors Selected Event Count Register. [a]
 c140PMUSERENRRW0x00000000Performance Monitors User Enable Register. [a]
 1PMINTENSETRWUNKPerformance Monitors Interrupt Enable Set Register. [a]
 2PMINTENCLRRWUNKPerformance Monitors Interrupt Event Clear Register. [a]
 3PMOVSSETRWUNKPerformance Monitors Overflow Flag Status Set Register. [a]
1c02L2CTLRRW0x00000000[b]L2 Control Register. See L2 Control Register, EL1.
 3L2ECTLRRW0x00000000L2 Extended Control Register. See L2 Extended Control Register, EL1.

[a] See the ARM® Architecture Reference Manual ARMv8 for more information.

[b] The reset value depends on the processor implementation and the state of the L2RSTDISABLE signal.


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