13.7.22. Trace ID Register 5

The TRCIDR5 characteristics are:


Returns how many resources the trace unit supports.

Usage constraints

There are no usage constraints.


Available in all configurations.


See the register summary in Table 13.3.

Figure 13.23 shows the TRCIDR5 bit assignments.

Figure 13.23. TRCIDR5 bit assignments

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Table 13.25 shows the TRCIDR5 bit assignments.

Table 13.25. TRCIDR5 bit assignments


Indicates whether the reduced function counter is implemented. This value is:


Reduced function counter is not supported.


Indicates the number of counters available for tracing. This value is:


Two counters are available.


Indicates the number of sequencer states implemented. This value is:


Four sequencer states are implemented.


Reserved, res0.


Indicates whether low power state override is supported. This value is:


Low power state override is not supported.


Indicates whether ATB triggers are supported. This value is:


ATB triggers are supported and the TRCEVENTCTL1R.ATBTRIG field is implemented.


Trace ID width. This value is:


A 7-bit trace ID width is supported. This defines the width of the TRCTRACEIDR.TRACEID field.


The CoreSight ATB requires a 7-bit trace ID width.


Reserved, res0.


Indicates the number of external input select resources are implemented. If NUMEXTINSEL is 0, NUMEXTIN must also be 0. This value is:


Four external input select resources are implemented.


Indicates the number of external inputs are implemented. This value is:


110 external inputs are implemented.

The TRCIDR5 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x1F4.

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