13.7.22. Trace ID Register 5

The TRCIDR5 characteristics are:

Purpose

Returns how many resources the trace unit supports.

Usage constraints

There are no usage constraints.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 13.3.

Figure 13.23 shows the TRCIDR5 bit assignments.

Figure 13.23. TRCIDR5 bit assignments

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Table 13.25 shows the TRCIDR5 bit assignments.

Table 13.25. TRCIDR5 bit assignments

BitsNameFunction
[31]REDFUNCNTR

Indicates whether the reduced function counter is implemented. This value is:

0

Reduced function counter is not supported.

[30:28]NUMCCNTR

Indicates the number of counters available for tracing. This value is:

0b010

Two counters are available.

[27:25]NUMSEQSTATE

Indicates the number of sequencer states implemented. This value is:

0b100

Four sequencer states are implemented.

[24]-

Reserved, res0.

[23]LPOVERRIDE

Indicates whether low power state override is supported. This value is:

0

Low power state override is not supported.

[22]ATBTRIG

Indicates whether ATB triggers are supported. This value is:

1

ATB triggers are supported and the TRCEVENTCTL1R.ATBTRIG field is implemented.

[21:16]TRACEIDSIZE

Trace ID width. This value is:

0x07

A 7-bit trace ID width is supported. This defines the width of the TRCTRACEIDR.TRACEID field.

Note

The CoreSight ATB requires a 7-bit trace ID width.

[15:12]-

Reserved, res0.

[11:9]NUMEXTINSEL

Indicates the number of external input select resources are implemented. If NUMEXTINSEL is 0, NUMEXTIN must also be 0. This value is:

0b100

Four external input select resources are implemented.

[8:0]NUMEXTIN

Indicates the number of external inputs are implemented. This value is:

0b001101110

110 external inputs are implemented.


The TRCIDR5 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x1F4.

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