13.7.16. Implementation Defined Register 0

The TRCIMSPEC0 characteristics are:


TRCIMSPEC0 is partially implemented for the future implementation of up to eight implementation defined registers so that a debugger can implement a general mechanism for detecting the implementation defined registers. This register must be implemented.

Usage constraints

There are no usage constraints.


Available in all configurations.


A 32-bit RW trace register. This register is reset by a trace unit reset.

See the register summary in Table 13.3.

Figure 13.17 shows the TRCIMSPEC0 bit assignments.

Figure 13.17. TRCIMSPEC0 bit assignments

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Table 13.19 shows the TRCIMSPEC0 bit assignments.

Table 13.19. TRCIMSPEC0 bit assignments


Reserved, res0.

[7:4]ENEN is res0 when the SUPPORT field is 0b0000.

Indicates whether the implementation supports implementation defined features. This value is:


No implementation defined features are supported.

The TRCIMSPEC0 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x1C0.

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