4.4.14. c14 registers

Table 4.95 shows the System registers when CRn is C14 and the processor is in AArch32 state. See the ARM® Architecture Reference Manual ARMv8 for more information about these registers.

Table 4.95. c14 register summary

op1CRmop2NameTypeResetDescription
0c00CNTFRQRW [a]UNKTimer Counter Frequency register
 c10CNTKCTLRW-[b]EL1 Timer Control register
 c20CNTP_TVALRWUNKEL1 Physical Timer TimerValue register
 1CNTP_CTLRW-[c]EL1 Physical Timer Control register
 c30CNTV_TVALRWUNKVirtual Timer TimerValue register
 1CNTV_CTLRW-[c]Virtual Timer Control register
 c80PMEVCNTR0RWUNKPerformance Monitors Event Count Registers
  1PMEVCNTR1
  2PMEVCNTR2
  3PMEVCNTR3
  4PMEVCNTR4
  5PMEVCNTR5
 c120PMEVTYPER0RWUNKPerformance Monitors Event Type Registers
  1PMEVTYPER1
  2PMEVTYPER2
  3PMEVTYPER3
  4PMEVTYPER4
  5PMEVTYPER5
 c157PMCCFILTRRW0x00000000Performance Monitors Cycle Count Filter Register
4c10CNTHCTLRW-[d]EL2 Timer Control register
 c20CNTHP_TVALRWUNKEL2 Physical Timer TimerValue register
 1CNTHP_CTLRW-[c]EL2 Physical Timer Control register

[a] Ar EL3(S) only, otherwise it is RO.

[b] The reset value for bits[9:8, 2:0] is 0b00000.

[c] The reset value for bit[0] is 0.

[d] The reset value for bit[2] is 0 and for bits[1:0] is 0b11.


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