4.4.12. c12 registers

Table 4.93 shows the System registers when CRn is c12 and the processor is in AArch32 state.

Table 4.93. c12 register summary

op1CRmop2NameTypeResetDescription
0c00VBARRW0x00000000[a]Vector Base Address Register. [b]
 1MVBARRWUNKMonitor Vector Base Address Register. [b]
 2RMRRW0x00000000[c]Reset Management Register. See Reset Management Register, EL3.
 c10ISRROUNKInterrupt Status Register. [b]
4c00HVBARRWUNKHyp Vector Base Address Register. [b]

[a] The reset value is 0x00000000 for the Secure copy of the register. You must program the Non-secure copy of the register with the required initial value, as part of the processor boot sequence.

[b] See the ARM® Architecture Reference Manual ARMv8 for more information.

[c] The reset value of bit[0] depends on the AA64nAA32 signal. Table 4.93 assumes this signal is LOW.


Copyright © 2013, 2014 ARM. All rights reserved.ARM DDI 0488D
Non-ConfidentialID012914