4.4.1. c0 registers

Table 4.82 shows the CP15 System registers when CRn is c0 and the processor is in AArch32 state.

Table 4.82. c0 register summary

op1CRmop2NameTypeResetDescription
0c00MIDRRO0x411FD071Main ID Register. See Main ID Register, EL1.
  1CTRRO0x8444C004Cache Type Register. See Cache Type Register, EL0.
  2TCMTR-0x00000000TCM Type Register.
  3TLBTRRO0x00000000TLB Type Register.
  4, 7MIDRRO0x411FD071Aliases of Main ID Register, Main ID Register, EL1.
  5MPIDRRO0x80000003[a]Multiprocessor Affinity Register.
  6REVIDRRO0x00000000Revision ID Register. See Revision ID Register, EL1.
 c10ID_PFR0RO0x00000131Processor Feature Register 0. See AArch32 Processor Feature Register 0, EL1.
  1ID_PFR1RO0x00011011[b]Processor Feature Register 1. See AArch32 Processor Feature Register 1, EL1.
  2ID_DFR0RO0x03010066Debug Feature Register 0. See AArch32 Debug Feature Register 0, EL1.
  3ID_AFR0RO0x00000000Auxiliary Feature Register 0. See AArch32 Auxiliary Feature Register 0, EL1.
  4ID_MMFR0RO0x10101105Memory Model Feature Register 0. See AArch32 Memory Model Feature Register 0, EL1.
  5ID_MMFR1RO0x40000000Memory Model Feature Register 1. See AArch32 Memory Model Feature Register 1, EL1.
  6ID_MMFR2RO0x01260000Memory Model Feature Register 2. See AArch32 Memory Model Feature Register 2, EL1.
  7ID_MMFR3RO0x02102211Memory Model Feature Register 3. See AArch32 Memory Model Feature Register 3, EL1.
 c20ID_ISAR0RO0x02101110Instruction Set Attribute Register 0. See AArch32 Instruction Set Attribute Register 0, EL1.
  1ID_ISAR1RO0x13112111Instruction Set Attribute Register 1. See AArch32 Instruction Set Attribute Register 1, EL1.
  2ID_ISAR2RO0x21232042Instruction Set Attribute Register 2. See AArch32 Instruction Set Attribute Register 2, EL1.
  3ID_ISAR3RO0x01112131Instruction Set Attribute Register 3. See AArch32 Instruction Set Attribute Register 3, EL1.
  4ID_ISAR4RO0x00011142Instruction Set Attribute Register 4. See AArch32 Instruction Set Attribute Register 4, EL1.
  5ID_ISAR5RO0x00010001[c]Instruction Set Attribute Register 5. See AArch32 Instruction Set Attribute Register 5, EL1.
1c00CCSIDRROUNKCache Size ID Register. See Cache Size ID Register, EL1.
  1CLIDRRO0x0A200023Cache Level ID Register. See Cache Level ID Register, EL1.
  7AIDR-0x00000000Auxiliary ID Register. See Auxiliary ID Register, EL1.
2c00CSSELRRWUNKCache Size Selection Register. See Cache Size Selection Register, EL1.
4c00VPIDRRW-[d]Virtualization Processor ID Register. See Virtualization Processor ID Register, EL2.
  5VMPIDRRO-[e]Virtualization Multiprocessor ID Register. See Virtualization Multiprocessor ID Register.

[a] The reset value depends on the primary inputs, CLUSTERIDAFF1 and CLUSTERIDAFF2, and the number of processors that the MPCore device implements. The value shown is for a four processor implementation, with CLUSTERIDAFF1 and CLUSTERIDAFF2 set to zero.

[b] The reset value depends on the primary input GICCDISABLE. The value shown assumes the GICCDISABLE signal is tied HIGH.

[c] The reset value is 0x00011121 if the Cryptography engine is implemented.

[d] The reset value is the value of the Main ID Register.

[e] The reset value is the value of the Multiprocessor Affinity Register.


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