4.4.2. c1 registers

Table 4.83 shows the System registers when CRn is c1 and the processor is in AArch32 state.

Table 4.83. c1 register summary

op1CRmop2NameTypeResetDescription
0c00SCTLRRW0x00C50838[a]System Control Register.
 1ACTLR-0x00000000Auxiliary Control Register. See Auxiliary Control Register, EL3.
 2CPACRRW0x00000000Architectural Feature Access Control Register.
 c10SCRRW0x00000000Secure Configuration Register.
 1SDERRW0x00000000Secure Debug Enable Register. [b]
 2NSACRRW [c]0x00000000Non-secure Access Control Register.
 c31SDCRRW0x00000000Secure Debug Configuration Register.
4c00HSCTLRRW0x30C50838Hyp System Control Register. [b]
 1HACTLRRW0x00000000Hyp Auxiliary Control Register. See Auxiliary Control Register, EL2.
 c10HCRRW0x00000000Hyp Configuration Register.
 1HDCRRW0x00000006[d]Hyp Debug Control Register.
 2HCPTRRW0x000033FFHyp Architectural Feature Trap Register.
 3HSTRRW0x00000000Hyp System Trap Register. See Hypervisor System Trap Register.
 4HCR2RW0x00000000Hyp Configuration Register 2.
 7HACRRW0x00000000Hyp Auxiliary Configuration Register.

[a] The reset value depends on primary input, CFGEND. The value shown assumes this signal is set to zero.

[b] See the ARM® Architecture Reference Manual ARMv8 for more information.

[c] RO at EL2 and EL0(NS).

[d] The reset value for bit[7] is UNK.


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