7.7.2. Interface modes

The ACE and CHI coherent interconnect interfaces can be configured through input signals to change the interface behavior. The multiprocessor implements the following configuration signals:

SYSBARDISABLE

SYSBARDISABLE controls issuing barrier transactions on the coherent interconnect.

When SYSBARDISABLE is deasserted, barriers are broadcast on the coherent interconnect as a Memory Barrier or Synchronization Barrier for an ACE interface, or an EOBarrier or ECBarrier for a CHI interface.

When SYSBARDISABLE is asserted, barriers are not broadcast on the coherent interconnect. Barriers are enforced internally to the Cortex-A57 MPCore processor by observing completion of transactions through the Read data channel and Write response channel for an ACE interface, or the RXDAT data channel and RXRSP response channel for a CHI interface. Systems that use this mode must ensure that ACE write responses or CHI RXRSP completion responses guarantee that the transaction has been globally observed and that barrier broadcasts are not required for any other system functionality.

For ACE configurations that require AXI3 compatibility you must:

  • Assert SYSBARDISABLE.

  • Deassert BROADCASTINNER.

  • Deassert BROADCASTOUTER.

  • Deassert BROADCASTCACHEMAINT.

BROADCASTINNER

BROADCASTINNER controls issuing coherent transactions targeting the Inner Shareable domain on the coherent interconnect. When BROADCASTINNER is asserted, the multiprocessor is considered to be part of an Inner Shareable domain that extends beyond the processor and any transaction that requires coherency with other masters in this domain is broadcast on the ACE or CHI interface.

When BROADCASTINNER is asserted, BROADCASTOUTER must also be asserted. In this configuration, coherent masters can share memory in the Inner or Outer Shareable domains.

When BROADCASTINNER is deasserted, the multiprocessor does not issue DVM requests on the ACE AR channel or CHI TXREQ channel.

BROADCASTOUTER

BROADCASTOUTER controls issuing coherent transactions targeting the outer shareability domain on the coherent interconnect. When BROADCASTOUTER is asserted, the multiprocessor is considered to be part of the Outer Shareable domain and any transaction that requires coherency with other masters in this domain is broadcast on the ACE or CHI interface.

It is possible to assert BROADCASTOUTER without asserting BROADCASTINNER. This selects a configuration that limits coherent masters to sharing memory only in the outer shareability domain. However, processors within the multiprocessor can still share memory in the Inner Shareable domain.

When BROADCASTOUTER is deasserted, BROADCASTINNER must also be deasserted.

When BROADCASTINNER and BROADCASTOUTER are both deasserted, the multiprocessor does not issue coherent read or write requests on the ACE AR and AW channels, or the CHI TXREQ channel.

BROADCASTCACHEMAINT

BROADCASTCACHEMAINT controls issuing cache maintenance transactions, such as CleanShared and CleanInvalid, on the coherent interconnect. When BROADCASTCACHEMAINT is asserted, cache maintenance instructions might cause cache maintenance transactions on ACE or CHI interconnect. The cache maintenance transactions are broadcast even if the memory location is Non-shareable or when the BROADCASTINNER or BROADCASTOUTER signals normally prevent such a broadcast. This configuration allows the management of an external L3 cache that might cache Non-shareable data.

When BROADCASTCACHEMAINT is deasserted, only those cache maintenance transactions required for coherency as determined by Inner and Outer shareability and the BROADCASTINNER and BROADCASTOUTER signals are issued on the coherent interconnect.

Systems that utilize a L3 cache that supports caching of Non-shareable memory must assert BROADCASTCACHEMAINT.

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