4.4.16. 64-bit registers

Table 4.97 gives a summary of the 64-bit wide System registers, accessed by the MCRR and MRRC instructions when the processor is in AArch32 state.

Table 4.97. 64-bit register summary

CRnop1CRmop2NameTypeResetDescription
-0c2-TTBR0RWUNKTranslation Table Base Register 0. [a]
-1c2-TTBR1RWUNKTranslation Table Base Register 1. [a]
-4c2-HTTBRRWUNKHyp Translation Table Base Register. [a]
-6c2-VTTBRRWUNK[b]Virtualization Translation Table Base Register. [a]
-0c7-PARRWUNKPhysical Address Register.
-0c9-PMCCNTRRW-[c]Performance Monitors Cycle Count Register. [a]
-0c14-CNTPCTROUNKPhysical Timer Count register. [a]
-1c14-CNTVCTROUNKVirtual Timer Count register. [a]
-2c14-CNTP_CVALRWUNKEL1 Physical Timer CompareValue register. [a]
-3c14-CNTV_CVALRWUNKVirtual Timer CompareValue register. [a]
-4c14-CNTVOFFRWUNKVirtual Timer Offset register. [a]
-6c14-CNTHP_CVALRWUNKEL2 Physical Timer CompareValue register. [a]
 0c15-CPUACTLRRW-[c]CPU Auxiliary Control Register. See CPU Auxiliary Control Register, EL1.
 1c15-CPUECTLRRW-[d]CPU Extended Control Register. See CPU Extended Control Register, EL1.
-2c15-CPUMERRSRRW-[e]CPU Memory Error Syndrome Register. See CPU Memory Error Syndrome Register, EL1.
-3c15-L2MERRSRRW-[e]L2 Memory Error Syndrome Register. See L2 Memory Error Syndrome Register, EL1.

[a] See the ARM® Architecture Reference Manual ARMv8 for more information.

[b] The reset value for bits[55:48] is zero.

[c] The reset value is zero.

[d] The reset value is 0x0000 001B 0000 0000.

[e] The reset value for bits[63,47:40,39:32,31] is zero.


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