13.7.31. Trace Integration Test ATB Control Register 2

The TRCITATBCTR2 characteristics are:


Enables the values of signal inputs to be read when bit[0] of the Integration Mode Control Register is set. See Trace Integration Mode Control register.

Usage constraints

There are no usage constraints.


Available in all configurations.


See the register summary in Table 13.3.

Figure 13.32 shows the TRCITATBCTR2 bit assignments.

Figure 13.32. TRCITATBCTR2 bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

Table 13.34 shows the TRCITATBCTR2 bit assignments.

Table 13.34. TRCITATBCTR2 bit assignments


Reserved, res0.


Returns the value of AFVALIDM input


Returns the value of ATREADYM input[a]

[a] To sample ATREADYM correctly from the multiprocessor signals, ATVALIDM must be asserted.

The TRCITATBCTR2 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xEF0.

Copyright © 2013, 2014 ARM. All rights reserved.ARM DDI 0488D