4.4.20. Fault and Exception handling registers

Table 4.101 shows the Fault handling registers in AArch32 state.

Table 4.101. Fault and Exception handling registers

NameCRnop1CRmop2TypeResetDescription
DFSRc50c00RWUNKData Fault Status Register.
IFSR  1RWUNKInstruction Fault Status Register. See Instruction Fault Status Register, EL2.
ADFSR  c10RWUNKAuxiliary Data Fault Status Register. See Auxiliary Fault Status Register 0, EL1 and EL3.
AIFSR  1RWUNKAuxiliary Instruction Fault Status Register. See Auxiliary Fault Status Register 1, EL1 and EL3.
HADFSR 4c10RWUNKHyp Auxiliary Data Fault Status Register. See Auxiliary Fault Status Register 0, EL2 and Hyp Auxiliary Data Fault Status Register.
HAIFSR 1RWUNKHyp Auxiliary Instruction Fault Status Register. See Auxiliary Fault Status Register 1, EL2 and Hyp Auxiliary Instruction Fault Status Register.
HSR c20RWUNKHyp Syndrome Register. See Exception Syndrome Register, EL2.
DFARc60c00RWUNKData Fault Address Register. [a]
IFAR  2RWUNKInstruction Fault Address Register. [a]
HDFAR 4c00RWUNKHyp Data Fault Address Register. [a]
HIFAR  2RWUNKHyp Instruction Fault Address Register. [a]
HPFAR  4RWUNKHyp IPA Fault Address Register. [a]
VBARc120c00RW0x00000000[b]Vector Base Address Register. [a]
MVBAR  1RWUNKMonitor Vector Base Address Register. [a]
RMR  2RW0x00000000[c]Reset Management Register. See Reset Management Register, EL3.
ISR  c10ROUNKInstruction Status Register. [a]
HVBAR 4c02RWUNKHyp Vector Base Address Register. [a]

[a] See the ARM® Architecture Reference Manual ARMv8 for more information.

[b] The reset value is 0x00000000 for the Secure copy of the register. You must program the Non-secure copy of the register with the required initial value, as part of the processor boot sequence.

[c] The reset value of bit[0] depends on the AA64nAA32 signal. Table 4.101 assumes this signal is LOW.


The Virtualization registers include additional fault handling registers. For more information see Virtualization registers.

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