4.3.70. Configuration Base Address Register, EL1

The CBAR_EL1 characteristics are:

Purpose

Holds the physical base address of the memory-mapped GIC CPU interface registers.

Usage constraints

The accessibility to the CBAR_EL1 by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-RORORORORO
Configurations

The CBAR_EL1 is:

  • Common to the Secure and Non-secure states.

  • A 64-bit register in AArch64 state.

Attributes

See the register summary in Table 4.15.

Figure 4.78 shows the CBAR_EL1 bit assignments.

Figure 4.78. CBAR_EL1 bit assignments

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Table 4.80 shows the CBAR_EL1 bit assignments.

Table 4.80. CBAR_EL1 bit assignments

BitsNameFunction
[63:44]-Reserved, res0
[43:18]PERIPHBASEThe primary input PERIPHBASE[43:18] determines the reset value
[17:0]-Reserved, res0

To access the CBAR_EL1 in AArch64 state, read the register with:

MRS <Xt>, s3_1_c15_c3_0; Read EL1 Configuration Base Address Register
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