4.3.35. Architectural Feature Trap Register, EL2

The CPTR_EL2 characteristics are:

Purpose

Controls trapping to EL2 for accesses to the CPACR, Trace functionality and registers associated with floating-point and Advanced SIMD execution. Controls EL2 access to this functionality.

Usage constraints

The accessibility of the CPTR_EL2 by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
---RWRWRW
Configurations

The CPTR_EL2 is:

Attributes

See the register summary in Table 4.13.

Figure 4.32 shows the CPTR_EL2 bit assignments.

Figure 4.32. CPTR_EL2 bit assignments

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Table 4.48 shows the CPTR_EL2 bit assignments.

Table 4.48.  CPTR_EL2 bit assignments

BitsNameFunction
[63:32]-

Reserved, res0.

[31]TCPAC

Traps direct access to CPACR from EL1 to EL2. The possible values are:

0

Access to CPACR is not trapped. This is the reset value.

1

Access to CPACR is trapped.

[30:21]-

Reserved, res0.

[20]TTAThis bit is res0. The processor does not support System register access to trace functionality.
[19:14]-

Reserved, res0.

[13:12]-

Reserved, res1.

[11]-

Reserved, res0.

[10]TFP

Traps instructions that access registers associated with floating-point and SIMD execution from a lower Exception level to EL2, unless trapped to EL1. The possible values are:

0

Instructions are not trapped. This is the reset value.

1

Instructions are trapped.

[9:0]-

Reserved, res1.


To access the CPTR_EL2 in AArch64 state, read or write the register with:

MRS <Xt>, CPTR_EL2; Read EL2 Architectural Feature Trap Register
MSR CPTR_EL2, <Xt>; Write EL2 Architectural Feature Trap Register
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