4.3.61. Reset Management Register, EL3

The RMR_EL3 characteristics are:

Purpose

Controls the Execution state that the processor boots into and allows request of a Warm reset.

Usage constraints

The accessibility to the RMR_EL3 by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
----RWRW
Configurations

The RMR_EL3 is

  • Common to the Secure and Non-secure states.

  • Architecturally mapped to the AArch32 RMR register.

Attributes

Write access to RMR_EL3 is disabled when the CP15SDISABLE signal is HIGH and EL3 is using AArch32.

See the register summary in Table 4.11.

Figure 4.53 shows the RMR_EL3 bit assignments.

Figure 4.53. RMR_EL3 bit assignments

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Table 4.70 shows the RMR_EL3 bit assignments.

Table 4.70. RMR_EL3 bit assignments

BitsNameFunction
[31:2]-

Reserved, res0.

[1]RR

Reset Request. The values are:

0

This is the reset value. It is set to zero by either a Cold or Warm reset.

1

Requests a Warm reset.

[0]AA64[a]

Determines the Execution state at processor boot time. The values are:

0

AArch32 state.

1

AArch64 state.

If software requests a Warm reset by setting RR=1 then it can use the AA64 bit to change Execution state.

[a] For a Cold reset, the value of this bit is set by the AA64nAA32 signal.


To access the RMR_EL3 in AArch64 state, read or write the register with:

MRS <Xt>, RMR_EL3; Read EL3 Reset Management Register
MSR RMR_EL3, <Xt>; Write EL3 Reset Management Register

To access the RMR, in AArch32 state, read or write the CP15 register with:

MRC p15, 0, <Rt>, c12, c0, 2; Read Reset Management Register
MCR p15, 0, <Rt>, c12, c0, 2; Write Reset Management Register
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