ARM Cortex-A57 MPCore Processor Technical Reference ManualRevision: r1p1
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4.3.45. Translation Table Base Register 0, EL3

The TTBR0_EL3 characteristics are:

Purpose

Holds the base address of the translation table for the stage 1 translation of memory accesses from EL3.

Usage constraints

The accessibility to the TTBR0_EL3 by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
----RWRW
Configurations

TTBR0_EL3 is mapped to the Secure AArch32 TTBR0 register.

Attributes

See the register summary in Table 4.3.

Figure 4.41 shows the TTBR0_EL3 bit assignments.

Figure 4.41. TTBR0_EL3 bit assignments

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Table 4.57 shows the TTBR0_EL3 bit assignments.

Table 4.57. TTBR0_EL3 bit assignments

BitsNameFunction
[63:48]-

Reserved, res0.

[47:10]BADDR

Translation table base address. Defining the translation table base address width.

[9:0]-

Reserved, UNK/res0.


To access the TTBR0_EL3 in AArch64 state, read or write the register with:

MRS <Xt>, TTBR0_EL3; Read EL3 Translation Table Base Register 0
MSR TTBR0_EL3, <Xt>; Write EL3 Translation Table Base Register 0
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