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Home > System Control > AArch64 register descriptions > Translation Table Base Register 0, EL3 |
The TTBR0_EL3 characteristics are:
Holds the base address of the translation table for the stage 1 translation of memory accesses from EL3.
The accessibility to the TTBR0_EL3 by Exception level is:
EL0 | EL1(NS) | EL1(S) | EL2 | EL3(SCR.NS = 1) | EL3(SCR.NS = 0) |
---|---|---|---|---|---|
- | - | - | - | RW | RW |
TTBR0_EL3 is mapped to the Secure AArch32 TTBR0 register.
See the register summary in Table 4.3.
Figure 4.41 shows the TTBR0_EL3 bit assignments.
Table 4.57 shows the TTBR0_EL3 bit assignments.
Table 4.57. TTBR0_EL3 bit assignments
Bits | Name | Function |
---|---|---|
[63:48] | - | Reserved, res0. |
[47:10] | BADDR | Translation table base address. Defining the translation table base address width. |
[9:0] | - | Reserved, UNK/res0. |
To access the TTBR0_EL3 in AArch64 state, read or write the register with:
MRS <Xt>, TTBR0_EL3; Read EL3 Translation Table Base Register 0 MSR TTBR0_EL3, <Xt>; Write EL3 Translation Table Base Register 0