4.3.68. CPU Memory Error Syndrome Register, EL1

The CPUMERRSR_EL1 characteristics are:

Purpose

Holds the number of memory errors that have occurred in the following L1 and L2 RAMs:

  • L1-I Tag RAM.

  • L1-I Data RAM.

  • L1-D Tag RAM.

  • L1-D Data RAM.

  • L2 TLB RAM.

A write of any value to the register updates the register to zero.

Usage constraints

The accessibility to the CPUMERRSR_EL1 by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-RWRWRWRWRW
Configurations

The CPUMERRSR_EL1 is:

  • Common to the Secure and Non-secure states.

  • A 64-bit read/write register.

  • Architecturally mapped to the AArch32 CPUMERRSR register.

Attributes

See the register summary in Table 4.15.

Figure 4.76 shows the CPUMERRSR_EL1 bit assignments.

Figure 4.76. CPUMERRSR_EL1 bit assignments

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Table 4.78 shows the CPUMERRSR_EL1 bit assignments.

Table 4.78. CPUMERRSR_EL1 bit assignments

BitsNameFunction
[63]Fatal

Fatal bit. This bit is set to 1 on the first memory error that caused a Data Abort. It is a sticky bit so that after it is set, it remains set until the register is written. The reset value is 0.

[62:48]-

Reserved, res0.

[47:40]

Other error count

This field is set to 0 on the first memory error and is incremented on any memory error that does not match the RAMID, bank, way, or index information in this register while the sticky Valid bit is set. The reset value is 0.

[39:32]Repeat error count

This field is set to 0 on the first memory error and is incremented on any memory error that exactly matches the RAMID, bank, way or index information in this register while the sticky Valid bit is set. The reset value is 0.

[31]Valid

Valid bit. This bit is set to 1 on the first memory error. It is a sticky bit so that after it is set, it remains set until the register is written. The reset value is 0.

[30:24]RAMID

RAM Identifier. Indicates the RAM, the first memory error occurred in. The possible values are:

0x00

L1-I Tag RAM.

0x01

L1-I Data RAM.

0x08

L1-D Tag RAM.

0x09

L1-D Data RAM.

0x18

L2 TLB RAM.

[23]-

Reserved, res0.

[22:18]Bank/Way

Indicates the bank or way of the RAM where the first memory error occurred.

[17:0]Index

Indicates the index address of the first memory error.


Note

  • If two or more memory errors in the same RAM occur in the same cycle, only one error is reported.

  • If two or more first memory error events from different RAMs occur in the same cycle, one of the errors is selected arbitrarily, while the Other error count field is only incremented by one.

  • If two or more memory error events from different RAMs, that do not match the RAMID, bank, way, or index information in this register while the sticky Valid bit is set, occur in the same cycle, the Other error count field is only incremented by one.

To access the CPUMERRSR_EL1 in AArch64 state, read or write the register with:

MRS <Xt>, S3_1_c15_c2_2 ; Read EL1 CPU Memory Error Syndrome Register
MSR S3_1_c15_c2_2 , <Xt>; Write EL1 CPU Memory Error Syndrome Register

To access the CPUMERRSR in AArch32 state, read or write the CP15 register with:

MRRC p15, 2, <Rt>, <Rt2>, c15; Read CPU Memory Error Syndrome Register
MCRR p15, 2, <Rt>, <Rt2>, c15; Write CPU Memory Error Syndrome Register
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