4.2.10. AArch64 reset registers

Table 4.11 shows the reset registers in AArch64 state.

Table 4.11. AArch64 reset registers

RVBAR_EL3RO- [a]64Reset Vector Base Address, EL3
RMR_EL3RW0x00000000[b]32Reset Management Register, EL3

[a] The reset value depends on the RVBARADDR signal. Bits[63:32] are reset to 0x00000000.

[b] For a Cold reset, the AA64nAA32 signal sets the value of bit[0]. Table 4.11 assumes this signal is LOW.

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