14.4.4. Media and VFP Feature Register 1, EL1

The MVFR1_EL1 characteristics are:

Purpose

The MVFR1_EL1 must be interpreted with the MVFR0_EL1 and the MVFR2_EL1 to describe the features provided by the Advanced SIMD and FP functions.

Usage constraints

The accessibility to the MVFR1_EL1 in AArch64 state by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-RORORORORO

The accessibility to the MVFR1 in AArch32 state by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-ConfigROConfigConfigRO
Configurations

The MVFR1_EL1 is:

  • Common to Secure and Non-secure states.

  • Architecturally mapped to AArch32 MVFR1 register.

Attributes

See the register summary in Table 14.2.

Figure 14.4 shows the MVFR1_EL1 bit assignments.

Figure 14.4. MVFR1_EL1 bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 14.6 shows the MVFR1_EL1 bit assignments.

Table 14.6. MVFR1_EL1 bit assignments 

BitsNameFunction
[31:28]SIMDFMAC

Indicates whether the Advanced SIMD or FP supports fused multiply accumulate operations:

0x1

Supported.

[27:24]FPHP

Indicates whether the FP supports half-precision floating-point conversion operations:

0x2

Supported.

[23:20]SIMDHP

Indicates whether the Advanced SIMD supports half-precision floating-point conversion operations:

0x1

Supported.

[19:16]SIMDSP

Indicates whether the Advanced SIMD supports single-precision floating-point operations:

0x1

Supported.

[15:12]SIMDInt

Indicates whether the Advanced SIMD supports integer operations:

0x1

Supported.

[11:8]SIMDLS

Indicates whether the Advanced SIMD supports load/store instructions:

0x1

Supported.

[7:4]FPDNaN

Indicates whether the FP hardware implementation supports only the Default NaN mode:

0x1

Hardware supports propagation of NaN values.

[3:0]FPFtZ

Indicates whether the FP hardware implementation supports only the Flush-to-zero mode of operation:

0x1

Hardware supports full denormalized number arithmetic.


To access the MVFR1_EL1 register, see Programmers model for Advanced SIMD and Floating-point.

Copyright © 2013, 2014 ARM. All rights reserved.ARM DDI 0488D
Non-ConfidentialID012914