4.3.20. AArch64 Instruction Set Attribute Register 0, EL1

The ID_AA64ISAR0_EL1 characteristics are:

Purpose

Provides information about the Cryptography Extension instruction set that the processor can support.

Note

  • The optional Cryptography engine is not included in the base product of the multiprocessor. ARM requires licensees to have contractual rights to obtain the Cortex-A57 MPCore multiprocessor Cryptography engine.

  • The SHA1, SHA2, and AES fields of ID_AA64ISAR0_EL1 are 0x0 if the Cryptography engine is not included or CRYPTODISABLE is HIGH.

Usage constraints

The accessibility to the ID_AA64ISAR0_EL1 by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-RORORORORO

The external debug accessibility to the ID_AA64ISAR0[63:32] and the ID_AA64ISAR0[31:0] by condition code is:

OffDLKOSLKEDADSLKDefault
-----RO

Table 10.1 describes the condition codes.

Configurations

The ID_AA64ISAR0_EL1 is architecturally mapped as follows:

  • [63:32] to external ID_AA64ISAR0[63:32] register.

  • [31:0] to external ID_AA64ISAR0[31:0] register.

Attributes

See the register summary in Table 4.1.

Figure 4.19 shows the ID_AA64ISAR0_EL1 bit assignments.

Figure 4.19. ID_AA64ISAR0_EL1 bit assignments

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Table 4.34 shows the ID_AA64ISAR0_EL1 bit assignments.

Table 4.34. ID_AA64ISAR0_EL1 bit assignments

BitsNameFunction
[63:20]-

Reserved, res0.

[19:16]CRC32Returns 0x1 to indicate that CRC32 instructions are implemented in AArch64 state.
[15:12]SHA2

Indicates whether SHA2 instructions are implemented in AArch64 state. The possible values are:

0x0

No SHA2 instructions implemented.

0x1

SHA256H, SHA256H2, SHA256U0, and SHA256U1 instructions implemented.

[11:8]SHA1

Indicates whether SHA1 instructions are implemented in AArch64 state. The possible values are:

0x0

No SHA1 instructions implemented.

0x1

SHA1C, SHA1P, SHA1M, SHA1SU0, and SHA1SU1 instructions implemented.

[7:4]AES

Indicates whether AES instructions are implemented in AArch64 state. The possible values are:

0x0

No AES instructions implemented.

0x2

AESE, AESD, AESMC, AESIMC and PMULL/PMULL2 instructions implemented.

[3:0]-

Reserved, res0.


To access the ID_AA64ISAR0_EL1 in AArch64 state, read the register with:

MRS <Xt>, ID_AA64ISAR0_EL1; Read AArch64 Instruction Set Attribute Register 0

The ID_AA64ISAR0[31:0] can be accessed through the memory-mapped interface and the external debug interface, offset 0xD30.

The ID_AA64ISAR0[63:32] can be accessed through the memory-mapped interface and the external debug interface, offset 0xD34.

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