4.3.11. AArch32 Memory Model Feature Register 3, EL1

The ID_MMFR3_EL1 characteristics are:

Purpose

Provides information about the implemented memory model and memory management support of the processor in AArch32.

Usage constraints

The ID_MMFR3_EL1 must be interpreted with:

  • ID_MMFR0_EL1.

  • ID_MMFR1_EL1.

  • ID_MMFR2_EL1.

The accessibility to the ID_MMFR3_EL1 by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-RORORORORO
Configurations

The ID_MMFR3_EL1 is:

  • Common to Secure and Non-secure states.

  • Architecturally mapped to the AArch32 ID_MMFR3 register.

Attributes

See the register summary in Table 4.1.

Figure 4.10 shows the ID_MMFR3_EL1 bit assignments.

Figure 4.10. ID_MMFR3_EL1 bit assignments

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Table 4.25 shows the ID_MMFR3_EL1 bit assignments.

Table 4.25. ID_MMFR3_EL1 bit assignments

BitsNameFunction
[31:28]Supersec

Indicates support for supersections. This value is:

0x0

Processor supports supersections.

[27:24]CMemSz

Indicates the physical memory size supported by the processor caches. This value is:

0x2

Processor caches support 40-bit physical address range.

[23:20]CohWalk

Indicates whether translation table updates require a clean to the point of unification. This value is:

0x1

Updates to the translation tables do not require a clean to the point of unification to ensure visibility by subsequent translation table walks.

[19:16]-

Reserved, res0.

[15:12]MaintBcst

Indicates whether cache, TLB and branch predictor operations are broadcast. This value is:

0x2

Cache, TLB and branch predictor operations affect structures according to shareability and defined behavior of instructions.

[11:8]BPMaint

Indicates the supported branch predictor maintenance operations. This value is:

0x2

Processor supports:

  • Invalidate all branch predictors.

  • Invalidate branch predictors by VA.

[7:4]CMaintSW

Indicates the supported cache maintenance operations by set/way. This value is:

0x1

Processor supports:

  • Invalidate data cache by set/way.

  • Clean data cache by set/way.

  • Clean and invalidate data cache by set/way.

[3:0]CMaintVA

Indicates the supported cache maintenance operations by VA. This value is:

0x1

Processor supports:

  • Invalidate data cache by VA.

  • Clean data cache by VA.

  • Clean and invalidate data cache by VA.

  • Invalidate Instruction Cache by VA.

  • Invalidate all Instruction Cache entries.


To access the ID_MMFR3_EL1 in AArch64 state, read the register with:

MRS <Xt>, ID_MMFR3_EL1; Read AArch32 Memory Model Feature Register 3

To access the ID_MMFR3 in AArch32 state, read the CP15 register with:

MRC p15, 0, <Rt>, c0, c1, 7; Read AArch32 Memory Model Feature Register 3
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