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Home > Advanced SIMD and Floating-point > AArch64 register descriptions > Floating-point Control Register |
The FPCR characteristics are:
Controls floating-point extension behavior.
The accessibility to the FPCR by Exception level is:
EL0 | EL1(NS) | EL1(S) | EL2 | EL3(SCR.NS = 1) | EL3(SCR.NS = 0) |
---|---|---|---|---|---|
RW | RW | RW | RW | RW | RW |
The FPCR is part of the Floating-point functional group.
The named fields in this register map to the equivalent fields in the AArch32 FPSCR.
See the register summary in Table 14.2.
Figure 14.1 shows the FPCR bit assignments.
Table 14.3 shows the FPCR bit assignments.
Table 14.3. FPCR bit assignments
Bits | Name | Function |
---|---|---|
[31:27] | - | Reserved, res0. |
[26] | AHP | Alternative half-precision control bit:
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[25] | DN | Default NaN mode control bit:
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[24] | FZ | Flush-to-zero mode control bit:
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[23:22] | RMode | Rounding Mode control field:
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[21:0] | - | Reserved, res0. |
To access FPCR in AArch64 state, read or write the register with:
MRS <Xt>, FPCR; Read Floating-point Control Register MSR FPCR, <Xt>; Write Floating-point Control Register