ARM Cortex-A57 MPCore Processor Technical Reference Manual: 14.4.1. Floating-point Control Register

The FPCR characteristics are:

Purpose

Controls floating-point extension behavior.

Usage constraints

The accessibility to the FPCR by Exception level is:

EL0	EL1(NS)	EL1(S)	EL2	EL3(SCR.NS = 1)	EL3(SCR.NS = 0)
RW	RW	RW	RW	RW	RW

Configurations

The FPCR is part of the Floating-point functional group.

The named fields in this register map to the equivalent fields in the AArch32 FPSCR.

Attributes

See the register summary in Table 14.2.

Figure 14.1 shows the FPCR bit assignments.

Figure 14.1. FPCR bit assignments

Table 14.3 shows the FPCR bit assignments.

Table 14.3. FPCR bit assignments

Bits	Name	Function
[31:27]	-	Reserved, res0.
[26]	AHP	Alternative half-precision control bit: 0 IEEE half-precision format selected. 1 Alternative half-precision format selected.
[25]	DN	Default NaN mode control bit: 0 NaN operands propagate through to the output of a floating-point operation. 1 Any operation involving one or more NaNs returns the Default NaN.
[24]	FZ	Flush-to-zero mode control bit: 0 Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard. 1 Flush-to-zero mode enabled.
[23:22]	RMode	Rounding Mode control field: `0b00` Round to Nearest (RN) mode. `0b01` Round towards Plus Infinity (RP) mode. `0b10` Round towards Minus Infinity (RM) mode. `0b11` Round towards Zero (RZ) mode.
[21:0]	-	Reserved, res0.

To access FPCR in AArch64 state, read or write the register with:

MRS <Xt>, FPCR; Read Floating-point Control Register
MSR FPCR, <Xt>; Write Floating-point Control Register

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