4.3.38. System Control Register, EL3

The SCTLR_EL3 characteristics are:

Purpose

Provides top-level control of the system, including its memory system at EL3 in AArch64 state.

Usage constraints

The accessibility of the SCTLR_EL3 by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
----RWRW
Configurations

The SCTLR_EL3 is:

  • A 32-bit register in AArch64 state.

  • Architecturally mapped to Secure AArch32 SCTLR register. See System Control Register for more information.

Attributes

See the register summary in Table 4.3.

Figure 4.34 shows the SCTLR_EL3 bit assignments.

Figure 4.34. SCTLR_EL3 bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.50 shows the SCTLR_EL3 bit assignments.

Table 4.50.  SCTLR_EL3 bit assignments

BitsNameFunction
[63:30]-

Reserved, res0.

[29:28]-

Reserved, res1.

[27:26]-

Reserved, res0.

[25]EE

Exception endianness. The values are:

0

Little-endian.

1

Big-endian.

The reset value depends on the primary input CFGEND.

[24]-

Reserved, res0.

[23:22]-

Reserved, res1.

[21:20]-

Reserved, res0.

[19]WXN

Force treatment of all memory regions with write permissions as XN. The values are:

0

Regions with write permissions are not forced to XN. This is the reset value.

1

Regions with write permissions are forced to XN.

[18]-

Reserved, res1.

[17]-

Reserved, res0.

[16]-

Reserved, res1.

[15:13]-

Reserved, res0.

[12]I

Global instruction cache enable. The values are:

0

Instruction caches disabled.

1

Instruction caches enabled.

[11]-

Reserved, res1.

[10:6]-

Reserved, res0.

[5:4]-

Reserved, res1.

[3]SA

Enables Stack Alignment check. The values are:

0

Disables Stack Alignment check. This is the reset value

1

Enables Stack Alignment check.

[2]C

Global enable for data and unified caches. The values are:

0

Disables data and unified caches. This is the reset value.

1

Enables data and unified caches.

[1]A

Enable Alignment fault check. The values are:

0

Disables Alignment fault checking. This is the reset value.

1

Enables Alignment fault checking.

[0]M

Global enable for the EL1 and EL0 stage 1 MMU. The values are:

0

Disables EL1 and EL0 stage 1 MMU. This is the reset value.

1

Enables EL1 and EL0 stage 1 MMU.


To access the SCTLR_EL3 in AArch64 state, read or write the register with:

MRS <Xt>, SCTLR_EL3; Read EL3 System Control Register
MSR SCTLR_EL3, <Xt>; Write EL3 System Control Register
Copyright © 2013, 2014 ARM. All rights reserved.ARM DDI 0488D
Non-ConfidentialID012914