4.3.18. AArch64 Processor Feature Register 0, EL1

The ID_AA64PFR0_EL1 characteristics are:

Purpose

Provides information on the exception handling of the processor in AArch64 state.

Usage constraints

The accessibility to the ID_AA64PFR0_EL1 by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-RORORORORO

The external debug accessibility to ID_AA64PFR0_EL1[63:32] and ID_AA64PFR0_EL1[31:0] by condition code is:

OffDLKOSLKEDADSLKDefault
-----RO

Table 10.1 describes the condition codes.

Configurations

The ID_AA64PFR0 is architecturally mapped as follows:

  • [63:32] to external ID_AA64PFR0[63:32] register.

  • [31:0] to external ID_AA64PFR0[31:0] register.

Attributes

See the register summary in Table 4.1.

Figure 4.17 shows the ID_AA64PFR0_EL1 bit assignments.

Figure 4.17. ID_AA64PFR0_EL1 bit assignments

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Table 4.32 shows the ID_AA64PFR0_EL1 bit assignments.

Table 4.32. ID_AA64PFR0_EL1 bit assignments

BitsNameFunction
[63:28]-

Reserved, res0.

[27:24]GIC system registers

Indicates support for the GIC System register interface. The possible values are:

0x0

No GIC System registers are supported. This is the reset value when GICCDISABLE is tied HIGH.

0x1

GICv3 System registers are supported. This is the reset value when GICCDISABLE is tied LOW.

[23:20]AdvSIMD

Returns 0x0 to indicate support for Advanced SIMD.

[19:16]FP

Returns 0x0 to indicate support for Floating-point.

[15:12]EL3Returns 0x2 to indicate EL3 supports AArch64 state or AArch32 state.
[11:8]EL2Returns 0x2 to indicate EL2 supports AArch64 state or AArch32 state.
[7:4]EL1Returns 0x2 to indicate EL1 supports AArch64 state or AArch32 state.
[3:0]EL0Returns 0x2 to indicate EL0 supports AArch64 state or AArch32 state.

To access the ID_AA64PFR0_EL1 in AArch64 state, read the register with:

MRS <Xt>, ID_AA64PFR0_EL1; Read AArch64 Processor Feature Register 0

The ID_AA64PFR0[31:0] can be accessed through the memory-mapped interface and the external debug interface, offset 0xD20.

The ID_AA64PFR0[63:32] can be accessed through the memory-mapped interface and the external debug interface, offset 0xD24.

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