4.3.27. Data Cache Zero ID, EL0

The DCZID_EL0 characteristics are:

Purpose

Indicates the block size written with byte values of 0 by the DC ZVA, Data Cache Zero by Address, system instruction.

Usage constraints

The accessibility of the DCZID_EL0 by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
RORORORORORO
Configurations

The DCZID_EL0 is a 32-bit register.

Attributes

See the register summary in Table 4.1.

Figure 4.25 shows the DCZID_EL0 bit assignments.

Figure 4.25. DCZID_EL0 bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.41 shows the DCZID_EL0 bit assignments.

Table 4.41. DCZID_EL0 bit assignments

BitsNameFunction
[63:5]-

Reserved, res0.

[4]DZP

Prohibit the DC ZVA instruction. The possible values are:

0

DC ZVA instruction permitted. This is the reset value.

1

DC ZVA instruction prohibited.

[3:0]BS

Returns 0x4 to indicate that the block size is 16 words.


To access the DCZID_EL0 in AArch64 state, read or write the register with:

MRS <Xt>, DCZID_EL0; Read Data Cache Zero ID Register
Copyright © 2013, 2014 ARM. All rights reserved.ARM DDI 0488D
Non-ConfidentialID012914