4.3.2. Multiprocessor Affinity Register, EL1

The MPIDR_EL1 characteristics are:

Purpose

Provides an additional processor identification mechanism for scheduling purposes in a multiprocessor system.

EDDEVAFF0 is a read-only copy of MPIDR_EL1[31:0] accessible from the external debug interface.

Usage constraints

The accessibility to the MPIDR_EL1 by Exception level is:

EL0EL1 (NS)EL1 (S)EL2EL3 (SCR.NS = 1)EL3 (SCR.NS = 0)
-RORORORORO

The external debug accessibility to the EDDEVAFF0 by condition code is:

OffDLKOSLKEDADSLKDefault
-----RO

Table 10.1 describes the condition codes.

Configurations

The MPIDR_EL1[31:0] is:

  • Architecturally mapped to the AArch32 MPIDR register. See Multiprocessor Affinity Register for more information.

  • Architecturally mapped to external EDDEVAFF0 register.

Attributes

See the register summary in Table 4.1.

Figure 4.2 shows the MPIDR_EL1 bit assignments.

Figure 4.2. MPIDR_EL1 bit assignments

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Table 4.17 shows the MPIDR_EL1 bit assignments.

Table 4.17. MPIDR_EL1 bit assignments

BitsNameFunction
[63:32]-

Reserved, res0.

[31]-

res1.

[30]U

Indicates a uniprocessor system, as distinct from processor 0 in a multiprocessor system. This value is:

0

Processor is part of a multiprocessor system.

[29:25]-

Reserved, res0.

[24]MT

Indicates whether the lowest level of affinity consists of logical processors that are implemented using a multi-threading type approach. This value is:

0

Performance of processors at the lowest affinity level is largely independent.

[23:16]Cluster ID Aff2

Indicates the value read in at reset, from the CLUSTERIDAFF2 configuration signal. It identifies an Cortex-A57 MPCore device in a system with more than one Cortex-A57 MPCore device present.

[15:8]Cluster ID Aff1

Indicates the value read in at reset, from the CLUSTERIDAFF1 configuration signal. It identifies an Cortex-A57 MPCore device in a system with more than one Cortex-A57 MPCore device present.

[7:2]-

Reserved, res0.

[1:0]CPU ID

Indicates the processor number in the Cortex-A57 MPCore device. The possible values are:

0x0

An MPCore device with one processor only.

0x0, 0x1

An MPCore device with two processors.

0x0, 0x1, 0x2

An MPCore device with three processors.

0x0, 0x1, 0x2, 0x3

An MPCore device with four processors.


To access the MPIDR_EL1 in AArch64 state, read the register with:

MRS <Xt>, MPIDR_EL1; Read Multiprocessor Affinity Register

The EDDEVAFF0 can be accessed through the memory-mapped interface and the external debug interface, offset 0xFA8.

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