4.3.47. Translation Control Register, EL3

The TCR_EL3 characteristics are:

Purpose

Controls translation table walks required for stage 1 translation of memory accesses from EL3 and holds cacheability and shareability information for the accesses.

Usage constraints

The accessibility of the TCR_EL3 by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
----RWRW
Configurations

The TCR_EL3 is architecturally mapped to the Secure AArch32 TTBCR register. See Translation Table Base Control Register for more information.

Attributes

See the register summary in Table 4.3.

Figure 4.43 shows the TCR_EL3 bit assignments.

Figure 4.43. TCR_EL3 bit assignments

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Table 4.59 shows the TCR_EL3 bit assignments.

Table 4.59.  TCR_EL3 bit assignments

BitsNameFunction
[31]-

Reserved, res1.

[30:24]-

Reserved, res0.

[23]-

Reserved, res1.

[22:21]-

Reserved, res0.

[20]TBI

Top Byte Ignored. Indicates whether the top byte of the input address is used for address match. The values are:

0

Top byte used in the address calculation.

1

Top byte ignored in the address calculation.

[19]-

Reserved, res0.

[18:16]PS

Physical Address size. The possible values are:

0b000

32 bits, 4GBytes.

0b001

36 bits, 64GBytes.

0b010

40 bits, 1TByte.

0b011

42 bits, 4TBytes.

0b100

44 bits, 16TBytes.

0b101

48 bits, 256TBytes.

[15]-

Reserved, res0.

[14]TGO

TTBR0_EL3 granule size. The values are:

0

4KByte.

1

64KByte.

[13:12]SH0

Shareability attribute for memory associated with translation table walks using TTBR0. The values are:

0b00

Non-shareable.

0b01

Reserved.

0b10

Outer Shareable.

0b11

Inner Shareable.

[11:10]ORGN0

Outer cacheability attribute for memory associated with translation table walks using TTBR0. The values are:

0b00

Normal memory, Outer Non-cacheable.

0b01

Normal memory, Outer Write-Back Write-Allocate Cacheable.

0b10

Normal memory, Outer Write-Through Cacheable.

0b11

Normal memory, Outer Write-Back no Write-Allocate Cacheable.

[9:8]IRGN0

Inner cacheability attribute for memory associated with translation table walks using TTBR0. The values are:

0b00

Normal memory, Inner Non-cacheable.

0b01

Normal memory, Inner Write-Back Write-Allocate Cacheable.

0b10

Normal memory, Inner Write-Through Cacheable.

0b11

Normal memory, Inner Write-Back no Write-Allocate Cacheable.

[7:6]-

Reserved, res0.

[5:0]T0SZ

Size offset of the memory region addressed by TTBR0. The region size is 2(32-TSIZE) bytes.


To access the TCR_EL3 in AArch64 state, read or write the register with:

MRS <Xt>, TCR_EL3; Read EL3 Translation Control Register
MRS TCR_EL3, <Xt>; Read EL3 Translation Control Register
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